SBAS948A December   2018  – June 2020 ADS52J65

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      Block Diagram
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Related Documentation
    2. 5.2 Trademarks
    3. 5.3 Electrostatic Discharge Caution
    4. 5.4 Glossary
  6. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 16-Bit Resolution, Idle SNR: 80 dBFS
  • 70 mW/Ch at 125 MSPS, 4-CH per Lane
  • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane
  • Full-Scale Input: 2 VPP
  • Full-Scale SNR: 78 dBFS at fin = 10 MHz
  • Full-Scale SFDR: –85 dBc at fin = 10 MHz
  • Analog Input –3 dB Bandwidth = 250 MHz
  • Maximum Input Signal Frequency for 2 VPP Input = 130 MHz
  • Fast and Consistent Overload Recovery
  • Advanced Digital Features
    • Automatic DC Offset Correction
    • Digital Average
  • Digital I/Q Demodulator
    • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
    • Data Output Rate Reduction After Decimation
    • 64 mW/Ch at 80 MSPS and Decimation = 2
    • On-Chip RAM With 32 Preset Profiles
  • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
    • 10-Gbps JESD Interface
    • Supports lane rate up to 12.8 Gbps for short trace length (< 5 Inch)
  • 64-Pin Non-Magnetic 9 × 9-mm Package