SBAS948A December 2018 – June 2020 ADS52J65
PRODUCTION DATA.
The 8-channel, 16-bit ADS52J65 analog-to-digital converter (ADC) uses CMOS process and innovative circuit techniques. It is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The device gives 80-dBFS idle SNR and 78-dBFS full-scale SNR at 5 MHz. The large input bandwidth of 250 MHz makes the device suitable for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, multi-channel data acquisition, flow cytometry, flow cytometer, and hematology analyzer. The ADC integrates an internal reference trimmed to match across devices.
ADS52J65 has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) output buffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8 Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9-mm × 9-mm VQFN allowing high system integration densities. ADS52J65 also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs.
The ADS52J65 is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C.
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| ADS52J65 | VQFN (64) | 9.00 mm × 9.00 mm |