SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values at TA = 25°C, minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
Analog Inputs
Full-scale differential input range Programmable 1.52 2 VPP
VCM Common-mode input Self-biased to AVDD5 / 2 AVDD5/2 V
RIN Input resistance, differential (dc) 100 Ω
CIN Input capacitance Estimated to ground from each AIN pin, excluding soldered package 4.3 pF
CMRR Common-mode rejection ratio Common mode signal = 125 MHz 40 dB
Internal Reference Voltage
VREF Reference voltage 1.98 2 2.02 V
Dynamic Accuracy
Resolution No missing codes 12 Bits
DNL Differential linearity error fIN = 125 MHz -1 ±0.4 2.5 LSB
INL Integral non- linearity error fIN = 125 MHz -4.5 ±1.5 4.5 LSB
Offset error default is trimmed near 0mV –2.5 0 2.5 mV
Offset temperature coefficient 0.02 mV/°C
Gain error ±5 %FS
Gain temperature coefficient 0.03 %FS/°C
Power Supply(1)
I(AVDD5) 5-V analog supply current (Bus A and B active) fIN = 125 MHz,
fS = 1 GSPS		 220 245 mA
5-V analog supply current (Bus A active) 225 255 mA
I(AVDD3) 3.3-V analog supply current (Bus A and B active) 205 234 mA
3.3-V analog supply current (Bus A active) 226 242 mA
I(DVDD3) 3.3-V digital supply current
(Bus A and B active)		 136 154 mA
3.3-V digital supply current
(Bus A active)		 72 85 mA
Total power dissipation
(BUS A and B active)		 2.2 2.5 W
Total power dissipation
(Bus A active)		 2 2.3 W
Total power dissipation ENPWD = logic High (sleep enabled) 13 50 mW
Wake-up time from sleep 1.8 ms
PSRR Power-supply rejection ratio 1MHz injected to each supply, measured without external decoupling 50 dB
Dynamic AC Characteristics
SNR Signal-to-noise ratio fIN = 125 MHz 54 58.5 dBFS
fIN = 600 MHz 53.5 58.3
fIN = 850 MHz 53 58
fIN = 1200 MHz 57.6
fIN = 1700 MHz 55.7
SFDR Spurious-free dynamic range fIN = 125 MHz 62 72 dBc
fIN = 600 MHz 60 70
fIN = 850 MHz 56 62.7
fIN = 1200 MHz 65.7
fIN = 1700 MHz 56
HD2 Second harmonic fIN = 125 MHz 62 78 dBc
fIN = 600 MHz 60 75
fIN = 850 MHz 56 62.5
fIN = 1200 MHz 66
fIN = 1700 MHz 56
HD3 Third harmonic fIN = 125 MHz 62 78 dBc
fIN = 600 MHz 60 72
fIN = 850 MHz 56 75
fIN = 1200 MHz 70
fIN = 1700 MHz 63
Worst harmonic/spur (other than HD2 and HD3) fIN = 125 MHz 62 80 dBc
fIN = 600 MHz 60 79
fIN = 850 MHz 56 79
fIN = 1200 MHz 66
fIN = 1700 MHz 64
THD Total Harmonic Distortion fIN = 125 MHz 60 71.7 dBc
fIN = 600 MHz 58 67
fIN = 850 MHz 55 66.5
fIN = 1200 MHz 63.8
fIN = 1700 MHz 55.7
SINAD Signal-to-noise and distortion fIN = 125 MHz 53 57 dBFS
fIN = 600 MHz 52.4 56.8
fIN = 850 MHz 50.8 55.8
fIN = 1200 MHz 56.6
fIN = 1700 MHz 52.7
Two-tone SFDR fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, each tone at –7 dBFS 74.6 dBFS
fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, each tone at –11 dBFS 77.9
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, each tone at –7 dBFS 68.3
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, each tone at –11 dBFS 73.7
ENOB Effective number of bits (using SINAD in dBFS) fIN = 125 MHz 8.52 9.55 Bits
fIN = 600 MHz 8.42 9.29
fIN = 850 MHz 8.16 9.23
RMS idle-channel noise Inputs tied to common-mode 1.41 LSB rms
60.2 dBFS
(1) All power values assume LVDS output current is set to 3.5 mA.