SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Interleaving Adjustments

Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset Adjustments
Resolution 9 Bits
LSB magnitude at full scale range of 2VPP 120 µV
DNL Differential linearity error -2.5 2.5 LSB
INL Integral Non-Linearity error -3 3 LSB
Recommended Min Offset Setting from default offset value, to maintain AC performance -8 mV
Recommended Max Offset Setting 8 mV
Gain Adjustments
Resolution 12 Bits
LSB magnitude 120 µV
DNL Differential linearity error -4 -1.2, +0.5 4 LSB
INL Integral Non-Linearity error -8 -2, +1 8 LSB
Min Gain Setting 1.52 VPP
Max Gain Setting 2 VPP
Input Clock Fine Phase Adjustment
Resolution 6 Bits
LSB magnitude 116 fs
DNL Differential linearity error -2 2.5 LSB
INL Integral Non-Linearity error -2.5 4 LSB
Max Fine Clock Skew setting 7.4 ps
Input Clock Coarse Phase Adjustment
Resolution 5 Bits
LSB magnitude 2.4 ps
DNL Differential linearity error -1 1 LSB
INL Integral Non-Linearity error -1 5 LSB
Max Coarse Clock Skew setting 73 ps
ADS5400-SP single_bus_las611.gif
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.
Figure 1. Single Bus Mode
ADS5400-SP dual_bus_alig_las611.gif
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.
Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2
ADS5400-SP dual_bus_stg_las611.gif
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.
Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2
ADS5400-SP sing_bus4_las611.gif
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.
Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4
ADS5400-SP dual_stg4_las611.gif
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.
Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4