SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Typical values at TA = 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
LVDS Digital Outputs (DATA, OVR/SYNCOUT, CLKOUT)
VOD Differential output voltage (±) Terminated 100 Ω differential 247 350 454 mV
VOC Common mode output voltage 1.125 1.25 1.375 V
LVDS Digital Inputs (RESET)
VID Differential input voltage (±) Each input pin 175 350 mV
VIC Common mode input voltage 0.1 1.25 2.4 V
RIN Input resistance 100 Ω
CIN Input capacitance Each pin to ground 3.7 pF
Digital Inputs (SCLK, SDIO, SDENB)
VIH High level input voltage 2 AVDD3 + 0.3 V
VIL Low level input voltage 0 0.8 V
IIH High level input current ±1 μA
IIL Low level input current ±1 μA
CIN Input capacitance 2.9 pF
Digital Inputs ( ENEXTREF, ENPWD, ENA1BUS)
VIH High level input voltage 2 AVDD5 + 0.3 V
VIL Low level input voltage 0 0.8 V
IIH High level input current ~40kΩ internal pull-down 125 μA
IIL Low level input current 20 μA
CIN Input capacitance 2.9 pF
Digital OutputS (SDIO, SDO)
VOH High level output voltage IOH = 250 µA 2.8 V
VOL Low level output voltage IOL = 250 µA 0.4 V
Clock Inputs
RIN Differential input resistance CLKINP, CLKINN 100 130 190 Ω
CIN Input capacitance Estimated to ground from each CLKIN pin, excluding soldered packaged 4.8 pF