The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS54J54 | VQFN (64) | 9.00mm x 9.00mm |
Changes from * Revision (January 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT OR REFERENCE | |||
INAP, INAM | 63, 62 | I | Differential analog input for channel A |
INBP, INBM | 58, 59 | I | Differential analog input for channel B |
INCP, INCM | 18, 19 | I | Differential analog input for channel C |
INDP, INDM | 23, 22 | I | Differential analog input for channel D |
VCM | 16 | O | Common mode output voltage to bias analog inputs, Vcm = 2.0 V |
VREF | 15 | O | Voltage reference output. A 0.1-µF bypass capacitor to ground close to the pin is recommended |
CLOCK/SYNC | |||
CLKINP, CLKINM | 9, 8 | I | Differential clock input for channel |
SYSREFABP, SYSREFABM | 6, 5 | I | LVDS input with internal 100-Ω termination. External SYSREF input for channels A, B, C, and D |
SYSREFCDP, SYSREFCDM | 11, 12 | I | LVDS input with internal 100-Ω termination. External SYSREF input for channels C and D if output rate of channel A/B is different from channel C/D. |
CONTROL OR SERIAL | |||
ENABLE | 14 | I | Chip enable. Active high. Power down functionality can be configured through SPI register setting and exercised using the ENABLE pin. Internal 51-kΩ pulldown resistor. |
SCLK | 3 | I | Serial interface clock input |
SDATA | 2 | I/O | Bidirectional serial data in 3-pin mode. In 4-pin interface, the SDATA pin is an input only. |
SDENb | 4 | I | Serial interface enable |
SDOUT | 1 | O | Serial interface data output |
SRESETb | 13 | I | Hardware reset. Active low. Initializes internal registers during high to low transition. This pin has an internal 51-kΩ pullup resistor. |
DATA OUTPUT INTERFACE | |||
DA[0,1]P, DA[0,1]M | 55, 54, 52, 51 | O | JESD204B output interface for channel A |
DB[0,1]P, DB[0,1]M | 46, 45, 43, 42 | O | JESD204B output interface for channel B |
DC[0,1]P, DC[0,1]M | 26, 27, 29, 30 | O | JESD204B output interface for channel C |
DD[0,1]P, DD[0,1]M | 35, 36, 38, 39 | O | JESD204B output interface for channel D |
OVRA | 50 | I/O | Fast over-range indicator channel A. |
OVRB | 49 | O | Fast over-range indicator channel B. |
OVRC | 31 | I/O | Fast over-range indicator channel C. |
OVRD | 32 | O | Fast over-range indicator channel D. |
SYNCbABP, SYNCbABM | 47, 48 | I | SYNCb input for JESD204B interface for channel A/B, internal 100-Ω termination |
SYNCbCDP, SYNCbCDM | 34, 33 | I | SYNCb input for JESD204B interface for channel C/D, internal 100-Ω termination |
POWER SUPPLY | |||
AVDDC | 7, 10 | I | Clock 1.8-V power supply |
AVDD18 | 21, 24, 57, 60 | I | Analog 1.9-V power supply |
AVDD33 | 17, 20, 61, 64 | I | Analog 3.3-V power supply |
DVDD | 25, 56 | I | Digital 1.8-V power supply |
GND | PowerPAD™ | I | Ground |
IOVDD | 28, 37, 44, 53 | I | JESD204B output interface 1.8-V power supply |
PLLVDD | 40, 41 | I | PLL 1.8-V power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD33 | –0.3 | 3.6 | V |
AVDD18 | –0.3 | 2.1 | ||
AVDDC | –0.3 | 2.1 | ||
DVDD | –0.3 | 2.1 | ||
IOVDD | –0.3 | 2.1 | ||
PLLVDD | –0.3 | 2.1 | ||
Voltage between AGND and DGND | –0.3 | 0.3 | V | |
Voltage applied to input pins | INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM | –0.3 | 3 | V |
CLKINP, CLKINM | –0.3 | AVDD18 + 0.3 V | ||
SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM | –0.3 | AVDD18 + 0.3 V | ||
SYSREFABP, SYSREFABM, SYSREFCDP, SYSREFCDM | –0.3 | AVDD18 + 0.3 V | ||
SCLK, SDENb, SDATA, SRESETb, ENABLE | –0.3 | DVDD + 0.5 V | ||
Operating free-air temperature, TA | –40 | 85 | ºC | |
Operating junction temperature, TJ(2) | 125 | ºC | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
ADC clock frequency | 250 | 500 | MSPS | |||
Resolution | 14 | 14 | bits | |||
Supply | AVDD33 | 3.15 | 3.3 | 3.45 | V | |
AVDD18 | 1.8 | 1.9 | 2 | |||
AVDDC | 1.7 | 1.8 | 1.9 | |||
DVDD | 1.7 | 1.8 | 1.9 | |||
IOVDD | 1.7 | 1.8 | 1.9 | |||
PLLVDD | 1.7 | 1.8 | 1.9 | |||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | 125 | °C |
Thermal Metric(1) | RGC (64 PINS) | UNIT | |
---|---|---|---|
RΘJA | Junction-to-ambient thermal resistance | 23.5 | °C/W |
RΘJC(top) | Junction-to-case, top | 7.0 | °C/W |
RΘJB | Junction-to-board thermal resistance | 2.6 | °C/W |
φJT | Junction-to-top of package | 0.1 | °C/W |
φJB | Junction-to-board characterization parameter | 2.6 | °C/W |
RΘJC(bot) | Junction-to-case, bottom | 0.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
IAVDD33 | 3.3-V analog supply current | 500 | mA | ||||
IAVDD18 | 1.9-V analog supply current | 320 | mA | ||||
IAVDDC | 1.8-V clock supply current | 18 | mA | ||||
IDVDD | 1.8-V digital supply current | 4-channel decimation filter | 323 | mA | |||
4-channel bypass digital mode | 324 | ||||||
2-channel decimation filter, 2-channel bypass digital mode | 324 | ||||||
IIOVDD | I/O voltage supply current | 2 lanes per ADC | 373 | mA | |||
1 lane per ADC | 185 | ||||||
IPLLVDD | PLL voltage supply current | 42 | mA | ||||
Pdis | Total power dissipation | 4-channel bypass digital mode | 3.46 | 3.7 | W | ||
4-channel decimation filter | 3.34 | ||||||
4-channel decimation filter, 1 lane per ADC | 3.27 | ||||||
2-channel decimation filter, 2-channel bypass digital mode | 3.51 | ||||||
Deep sleep mode power | 791 | mW | |||||
Wake-up time from deep sleep mode | SNR > 60 dB | 1.4 | ms | ||||
Light sleep mode power | 1.68 | W | |||||
Wake-up time from light sleep mode | SNR > 60 dB | 8 | µs | ||||
ANALOG INPUTS | |||||||
Differential input full-scale | 1 | 1.25 | 1.5 | Vpp | |||
Input common mode voltage | VCM ± 50 mV | V | |||||
Input resistance | Differential at DC | 1 | kΩ | ||||
Input capacitance | Each input to GND | 2.75 | pF | ||||
VCM | Common mode voltage output | 2.18 | V | ||||
Analog input bandwidth (–3 dB) | 900 | MHz | |||||
INL | Integral nonlinearity | ±3 | LSB | ||||
DNL | Dynamic nonlinearity | –1 | ±0.9 | LSB | |||
Gain error | ±2.24% | ||||||
Offset error | ±1.91 | mV | |||||
CHANNEL-TO-CHANNEL ISOLATION | |||||||
Crosstalk(1) | Near channel | ƒIN = 170 MHz | 85 | dB | |||
Far channel | ƒIN = 170 MHz | 95 | |||||
CLOCK INPUT | |||||||
Input clock frequency | 250 | 2000(2) | MHz | ||||
Input clock amplitude | 0.4 | 1.5 | Vpp | ||||
Input clock duty cycle | 45% | 50% | 55% | ||||
Internal clock biasing | 0.9 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SNR | Signal-to-noise ratio | ƒIN = 10 MHz | 68.3 | dBFS | |||
ƒIN = 100 MHz | 68.2 | ||||||
ƒIN = 170 MHz | 67.2 | ||||||
ƒIN = 310 MHz | 67.6 | ||||||
ƒIN = 450 MHz | 66.8 | ||||||
HD2 | Second harmonic distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 85 | ||||||
ƒIN = 310 MHz | 85 | ||||||
ƒIN = 450 MHz | 75 | ||||||
HD3 | Third harmonic distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 85 | ||||||
ƒIN = 310 MHz | 85 | ||||||
ƒIN = 450 MHz | 85 | ||||||
SFDR
(Non-HD2, Non-HD3) |
Spur free dynamic range
(excluding HD2 and HD3) |
ƒIN = 10 MHz | 95 | dBc | |||
ƒIN = 100 MHz | 95 | ||||||
ƒIN = 170 MHz | 95 | ||||||
ƒIN = 310 MHz | 90 | ||||||
ƒIN = 450 MHz | 85 | ||||||
IMD3 | 2F1-F2, 2F2-F1, Ain = –7 dBFS | FIN = 169 and 171 MHz | 93 | dBFS |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SNR | Signal-to-Noise Ratio | Bypass Digital Mode (14 bit) | ƒIN = 10 MHz | 65.3 | dBFS | ||
ƒIN = 100 MHz | 65.2 | ||||||
ƒIN = 170 MHz | 61 | 64.9 | |||||
ƒIN = 370 MHz | 64.7 | ||||||
ƒIN = 450 MHz | 64.6 | ||||||
HD2 | Second Harmonic Distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 70 | 85 | |||||
ƒIN = 370 MHz | 75 | ||||||
ƒIN = 450 MHz | 75 | ||||||
HD3 | Third Harmonic Distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 70 | 85 | |||||
ƒIN = 370 MHz | 85 | ||||||
ƒIN = 450 MHz | 85 | ||||||
SFDR
(Non-HD2, Non-HD3) |
Spur Free Dynamic Range
(excluding HD2 and HD3) |
ƒIN = 10 MHz | 85 | dBFS | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 70 | 85 | |||||
ƒIN = 370 MHz | 83 | ||||||
ƒIN = 450 MHz | 83 | ||||||
IMD3 | 2F1-F2, 2F2-F1, Ain = –7 dBFS | fIN = 169 and 171 MHz | 87 | dBFS |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Aperture jitter, RMS | 98 | fs rms | |||
Data latency | 38 | Sample clock cycles | |||
Fast over-range (OVR) latency | 6 | ||||
tPDI | Clock aperture delay | 1.1 | ns |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
DIGITAL OUTPUTS: JESD204B INTERFACE (DA[0,1], DB[0,1], DC[0,1], DD[0,1]) | |||||
Output differential voltage, |VOD| | 450 | 577 | 750 | mV | |
Transmitter short circuit current | Transmitter terminals shorted to any voltage between –0.25 and 1.45 V | 45 | mA | ||
Single ended output impedance | 50 | Ω | |||
Output capacitance | Output capacitance inside the device, from either output to ground | 2 | pF | ||
Unit interval, UI | 5.0 Gbps | 200 | ps | ||
Rise and fall times | 110 | ps | |||
Output jitter | 57 | ps | |||
Serial output data rate | 5.0 | Gbps |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
DIGITAL INPUTS: SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM | |||||
High-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels | 1.2 | V | ||
Low-level input voltage | 0.4 | V | |||
High-level input current | 50 | µA | |||
Low-level input current | –50 | µA | |||
Input capacitance | 4 | pF | |||
DIGITAL OUTPUTS: SDOUT, OVRA, OVRB, OVRC, OVRD | |||||
High-level output voltage | ILoad = –100 µA | DVDD – 0.2 | DVDD | V | |
Low-level output voltage | 0.2 | V | |||
DIGITAL INPUTS:
SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M |
|||||
Input voltage VID | 250 | 350 | 450 | mV | |
Input common mode voltage VCM | 0.4 | 0.9 | 1.4 | V | |
tS_SYSREFxx | Referenced to rising edge of input clock | 100 | ps | ||
tH_SYSREFxx | Referenced to rising edge of input clock | 100 | ps |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | Power-on delay | Delay from power up to active-low RESET pulse | 3 | ms | ||
t2 | Reset pulse duration | Active-low RESET pulse duration | 20 | ns | ||
t3 | Register write delay | Delay from RESET disable to SDENb active | 100 | ns |
Fin = 10 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.29 dBFS | SFDR = 84.72 dBc |
Fin = 170 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.34 dBFS | SFDR = 91.62 dBc |
Fin = 230 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.16 dBFS | SFDR = 76.83 dBc |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Fin = 170 MHz |
1-lane 2x decimation | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 100 MHz |
SNR = 65.41 dBFS | SFDR = 83.25 dBc |
2-lane no decimation | Ain = –1 dBFS | Fin = 230 MHz |
SNR = 64.91 dBFS | SFDR = 83.29 dBc |
2-lane no decimation | Ain = –1 dBFS |
2-lane no decimation | Fin = 170 MHz | |
2-lane no decimation | Fin = 170 MHz | |
2-lane no decimation | Ain = –1 dBFS | |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz | ||
Fin = 100 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.40 dBFS | SFDR = 82.50 dBc |
Fin = 230 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.16 dBFS | SFDR = 76.83 dBc |
1-lane 2x decimation | Ain = –1 dBFS | |
1-lane 2x decimation | Fin = 170 MHz |
1-lane 2x decimation | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
AVDD18 = 1.9 V | AVDD33 = 3.3 V | Other supplies = 1.8 V |
Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 10 MHz |
SNR = 65.27 dBFS | SFDR = 86.63 dBc |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
SNR = 65.26 dBFS | SFDR = 90.42 dBc |
2-lane no decimation | Ain = –1 dBFS | |
Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS |
2-lane no decimation | Fin = 170 MHz | |
2-lane no decimation | Fin = 170 MHz | |
2-lane no decimation | Ain = –1 dBFS | |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane no decimation | Ain = –1 dBFS | Fin = 170 MHz |
The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel ADC. It supports the JESD204B serial interface with data rates up to 5.0 Gbps supporting 1 or 2 lanes per channel. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent SFDR over a large input frequency range with low power consumption.
Each channel has a digital filter in the data path as shown in Figure 54. The filter can be programmed as a low-pass or high-pass filter and the normalized frequency response of both filters is shown in Figure 55.
The decimation filter response has a 0.1-dB pass band ripple with approximately 41% pass-band bandwidth. The stop-band attenuation is approximately 40 dB.
The ADS54J54 provides a fast over-range indication on the OVRA, OVRB, OVRC, and OVRD pins. The fast OVR is triggered if the input voltage exceeds the programmable over-range threshold and is output after just 6 clock cycles, enabling a quicker reaction to an over-range event. The OVR threshold can be configured using SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the over-range threshold bits.
The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] / 8). After reset, the default value of the over-range threshold is set to 7 (decimal), which corresponds to a threshold of 1.12 dB below full scale (20 × log(7/8)).
OVR Setting (decimal) | OVR Threshold (dBFS) |
---|---|
1 | –18.1 |
2 | –12.0 |
3 | –8.5 |
4 | –6.0 |
5 | –4.1 |
6 | –2.5 |
7 (default) | –1.1 |
Because the fast over-range indicator is single-ended LVCMOS logic, the ADS54J54 device can be configured through the SPI register write to keep the over-range indicator asserted high for an extra one, two, or four clock cycles. This longer assertion of the signal ensures the processor can capture the over-range event.
The ADS54J54 device also provides the fast over-range indication bit in the JESD204B output data stream.
The ADS54J54 supports device subclass 1 with a maximum output data rate of 5 Gbps for each serial transmitter. It allows independent JESD204B format configuration for channel A and B and channel C and D.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. SYNCbAB input is used to control all the JESD204B SerDes blocks for channel A and B while SYNCbCD is used to control channel C and D. If the same LMFS configuration is used for all four channels, the SYNCbAB and SYNCbCD signals can be tied together externally and driven from the same source.
Depending on the channel output data rate, the JESD204B output interface can be operated with either 1 or 2 lanes per single channel. The JESD204B setup and configuration of the frame assembly parameters are controlled via SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The transport layer maps the channel output data into the selected JESD204B frame data format and manages if the channel output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNCb input signal. Optionally, data from the transport layer can be scrambled.
The ILA process is started by the receiving device by deasserting the SYNCb signal. Upon detecting a logic low on the SYNCbAB input pins, the ADS54J54 device starts transmitting comma (K28.5) characters on channels A and B to establish code group synchronization. Upon detecting a logic high on the SYNCbCD input pins, the ADS54J54 device starts transmitting comma (K28.5) characters on channels C and D to establish code group synchronization.
After synchronization is completed, the receiving device asserts the SYNCb signal and the ADS54J54 starts the ILA sequence with the next local multi-frame clock boundary. The ADS54J54 device transmits 4 multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J54 supports a RAMP, 1555/2AAA and different PRBS patterns. They can be enabled through SPI register write and are located in address 0x1D and 0x32/33.
The JESD204B standard defines the following parameters:
The ADS54J54 supports independent configuration of the JESD204B format for channel A and B and channel C and D. Table 2 lists the available JESD204B formats and valid ranges for the ADS54J54. The ranges are limited by the SerDes line rate and the maximum channel sample frequency.
L | M | F | S | HD | Max Channel Output Rate (MSPS) | Max ƒSerDes (Gsps) |
---|---|---|---|---|---|---|
8 | 4 | 1 | 1 | 1 | 500 | 5.0 |
4 | 4 | 2 | 1 | 0 | 250 | 5.0 |
The detailed frame assembly is shown in Table 3.
LMFS = 8411 | LMFS = 4421 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
Lane DA0 | A0[13:6] | A1[13:6] | A2[13:6] | A3[13:6] | A0[13:6] | A0[5:0], 00 | A1[13:6] | A1[5:0], 00 | A2[13:6] | A2[5:0], 00 |
Lane DA1 | A0[5:0], 00 | A1[5:0], 00 | A2[5:0], 00 | A3[5:0], 00 | ||||||
Lane DB0 | B0[13:6] | B1[13:6] | B2[13:6] | B3[13:6] | B0[13:6] | B0[5:0], 00 | B1[13:6] | B1[5:0], 00 | B2[13:6] | B2[5:0], 00 |
Lane DB1 | B0[5:0], 00 | B1[5:0], 00 | B2[5:0], 00 | B3[5:0], 00 | ||||||
Lane DC0 | C0[13:6] | C1[13:6] | C2[13:6] | C3[13:6] | C0[13:6] | C0[5:0], 00 | C1[13:6] | C1[5:0], 00 | C2[13:6] | C2[5:0], 00 |
Lane DC1 | C0[5:0], 00 | C1[5:0], 00 | C2[5:0], 00 | C3[5:0], 00 | ||||||
Lane DD0 | D0[13:6] | D1[13:6] | D2[13:6] | D3[13:6] | D0[13:6] | D0[5:0], 00 | D1[13:6] | D1[5:0], 00 | D2[13:6] | D2[5:0], 00 |
Lane DD1 | D0[5:0], 00 | D1[5:0], 00 | D2[5:0], 00 | D3[5:0], 00 |
Periodic: The SYSREF signal is always on. This mode is supported, but not recommended as the continuous SYSREF signal appears like an additional clock input, which can cause clock mixing spurs in the channel output spectrum.
Gapped-Periodic (recommended): A periodic SYSREF signal is presented to the ADS54J54 SYSREF inputs for a very short period of time. This configuration requires a DC-coupled SYSREF connection for proper operation. Most of the time the SYSREF signal is in a logic-low state, and thus cannot cause any glitches and spurs in the channel output spectrum.
Pulse/One Shot (recommended): A single SYSREF reset pulse is used to synchronize the ADS54J54. The ADS54J54 device requires a minimum of 3 SYSREF pulses to complete the synchronization phase. The SYSREF signal is in a logic-low state most of the time, and thus cannot cause any glitches and spurs in the channel output spectrum. Special attention should be given to ensure the single pulse meets required the SYSREF input setup and hold time.
The ADS54J54 provides several different options to interface it to the digital processor or processors. If the ADS54J54 device is operated in split sampling rate (2 channels at 500-MSPS output rate and 2 channels at 250-MSPS output rate), then it requires dual SYSREF (SYSREFAB and SYSREFCD) and dual SYNC (SYNCbAB and SYNCbCD).
Subclass 1 – Deterministic Latency: The device clock and synchronous SYSREF signal are provided by the timing unit to the ADS54J54 and the processor. The processor controls the SYNCb input signals for the JESD204B state machine for all four channels. In case the ADS54J54 is connected to two different processors, the differential SYNCb inputs of the ADS54J54 can be configured to two single-ended inputs where each pin controls the JESD204B state machine of the two corresponding channels.
Split Mode Operation: If the ADS54J54 device is operated with 2-channel output at 500 MSPS and 2-channel output at 250 MSPS, then dual SYSREF (SYSREFAB for channel A and B, SYSREFCD for channel C and D) as well as dual SYNC (SYNCbAB for channel A and B, SYNCbCD for channel C and D) is required to ensure normal operation because the JESD204B link configuration is different for the two channel pairs.
The ADS54J54 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high-impedance input across a wide frequency range to the external driving source, which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, which results in a more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 2 V using 500-Ω resistors, which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.3125 V) and (VCM – 0.3125 V), resulting in a 1.25-Vpp (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.
The ADS54J54 clock input can be driven differentially with a sine wave or LVPECL source with little or no difference in performance. The common mode voltage of the clock input is set to 0.9 V using internal 2-kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as possible to the clock inputs in order to minimize signal reflections and jitter degradation.
The ADS54J54 is equipped with two internal dividers on the clock input – one on channel AB and one on channel CD. The clock divider allows operation with a faster input clock simplifying the system clock distribution design. The clock dividers can be bypassed (/1) for operation with a 500-MHz clock while /2 option supports a maximum input clock of 1 GHz and the /4 option a maximum input clock frequency of 2 GHz. Different divider options can be selected for channel AB and channel CD clock output. By default the divider output of channel AB block is routed to all 4 channels but the configuration can be customized with different SPI register settings to use either the channel AB or CD divider blocks for any two channels.