10.1 Layout Guidelines
The Device EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 107. Some important points to remember during laying out the board are:
- Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk on-board, the analog inputs should exit the pinout in opposite directions, as shown in the reference layout of Figure 107 as much as possible.
- In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 107 as much as possible.
- Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pinout, the digital output traces should not be kept parallel to the analog input traces because this configuration may result in coupling from digital outputs to analog inputs and degrade performance. The digital sample data rate can be as high as 5.0 Gsps, so care must be taken to maintain the signal integrity of these signals. A low-loss dielectric circuit board is recommended or else these traces should be kept as short as possible. These traces should be kept away from the analog inputs ad n clock input to the device as well.
- At each power-supply pin, a 0.1-μF decoupling capacitor should be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-μF,
1-μF, and 0.1-μF capacitors can be kept close to the supply source.