SBAS706D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
The internal dc offset of the individual cores changes with temperature, resulting in fS / 4 and fS / 2 spurs appearing again in the spectrum at a different temperature.
Figure 144 shows a variation of the fS / 4 spur over temperature for a typical device.
NOTE:
The offset correction block was frozen at room temperature, then the temperature was varied from –40°C to +85°C.Although some systems can accept such a variation in the fS / 4 and fS / 2 spurs across temperature, other systems may require the internal dc offset profile to be calibrated with temperature. To achieve this calibration, the device provides an option to read the internal estimate values from the correction block for each of the interleaving cores and also to load the values back to the correction block. For calibration, after power up, a temperature sweep can be performed with the idle channel input and the internal dc offset can be read back using the ADCx_CORR_INT_EST register bits for salient temperature points. Then during operation, when temperature changes, the corresponding estimates can be externally loaded to the correction block using the ADCx_LOAD_EXT_EST register bits.
The dc offset corrector block is enabled by default. For a given channel, the device can disable and freeze the block, read the estimate of the block, and load the external estimate.
Table 77 lists an example of required SPI writes for reading an internal estimate of the dc offset correction block, and then loading the estimate back to the corrector.
STEP | ADDRESS (Hex)(1) | DATA (Hex) | COMMENT |
---|---|---|---|
Reading an internal estimate from both channels | 4-005 | 01 | This setting disables broadcast mode (channel A and B can be individually programmed) |
4-004 | 61 | Selects offset read page (61000000h) | |
4-003 | 00 | ||
4-002 | 00 | ||
4-001 | 00 | ||
Data from the offset read page can be read as below (keep the R/W bit = 1) | |||
E-074 | xx | Reading the internal estimate [7:0] for core 0, channel A on the SDOUT pin | |
E-075 | xx | Reading the internal estimate [10:8] for core 0, channel A on the SDOUT pin | |
E-076 | xx | Reading the internal estimate [7:0] for core 1, channel A on the SDOUT pin | |
E-077 | xx | Reading the internal estimate [10:8] for core 1, channel A on the SDOUT pin | |
E-078 | xx | Reading the internal estimate [7:0] for core 2, channel A on the SDOUT pin | |
E-079 | xx | Reading the internal estimate [10:8] for core 2, channel A on the SDOUT pin | |
E-07A | xx | Reading the internal estimate [7:0] for core 3, channel A on the SDOUT pin | |
E-07B | xx | Reading the internal estimate [10:8] for core 3, channel A on the SDOUT pin | |
F-074 | xx | Reading the internal estimate [7:0] for core 0, channel B on the SDOUT pin | |
F-075 | xx | Reading the internal estimate [10:8] for core 0, channel B on the SDOUT pin | |
F-076 | xx | Reading the internal estimate [7:0] for core 1, channel B on the SDOUT pin | |
F-077 | xx | Reading the internal estimate [10:8] for core 1, channel B on the SDOUT pin | |
F-078 | xx | Reading the internal estimate [7:0] for core 2, channel B on the SDOUT pin | |
F-079 | xx | Reading the internal estimate [10:8] for core 2, channel B on the SDOUT pin | |
F-07A | xx | Reading the internal estimate [7:0] for core 3, channel B on the SDOUT pin | |
F-07B | xx | Reading the internal estimate [10:8] for core 3, channel B on the SDOUT pin | |
Loading an external estimate to both channels | 6-069 | 01 | Enables the external correction bit located in the offset read page for channel A |
7-069 | 01 | Enables the external correction bit located in the offset read page for channel B | |
4-004 | 61 | Change page to offset load page (61000500h) | |
4-003 | 00 | ||
4-002 | 05 | ||
4-001 | 00 | ||
6-000 | xx | Loading the external estimate [7:0] for core 0, channel A through SPI writes | |
6-001 | xx | Loading the external estimate [10:8] for core 0, channel A through SPI writes | |
6-004 | xx | Loading the external estimate [7:0] for core 1, channel A through SPI writes | |
6-005 | xx | Loading the external estimate [10:8] for core 1, channel A through SPI writes | |
6-008 | xx | Loading the external estimate [7:0] for core 2, channel A through SPI writes | |
6-009 | xx | Loading the external estimate [10:8] for core 2, channel A through SPI writes | |
6-00C | xx | Loading the external estimate [7:0] for core 3, channel A through SPI writes | |
6-00D | xx | Loading the external estimate [10:8] for core 3, channel A through SPI writes | |
7-000 | xx | Loading the external estimate [7:0] for core 0, channel B through SPI writes | |
7-001 | xx | Loading the external estimate [10:8] for core 0, channel B through SPI writes | |
7-004 | xx | Loading the external estimate [7:0] for core 1, channel B through SPI writes | |
7-005 | xx | Loading the external estimate [10:8] for core 1, channel B through SPI writes | |
7-008 | xx | Loading the external estimate [7:0] for core 2, channel B through SPI writes | |
7-009 | xx | Loading the external estimate [10:8] for core 2, channel B through SPI writes | |
7-00C | xx | Loading the external estimate [7:0] for core 3, channel B through SPI writes | |
7-00D | xx | Loading the external estimate [10:8] for core 3, channel B through SPI writes |