SBAS706D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRL K | 0 | 0 | TESTMODE EN | FLIP ADC DATA | LANE ALIGN | FRAME ALIGN | TX LINK DIS |
R/W-0h | W-0h | W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CTRL K | R/W | 0h | Enable bit for a number of frames per multi frame.
0 = Default is five frames per multi frame 1 = Frames per multi frame can be set in register 06h |
6-5 | 0 | W | 0h | Must write 0 |
4 | TESTMODE EN | R/W | 0h | This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled 1 = Test mode enabled |
3 | FLIP ADC DATA | R/W | 0h | 0 = Normal operation
1 = Output data order is reversed: MSB to LSB. |
2 | LANE ALIGN | R/W | 0h | This bit inserts the lane alignment character (K28.3) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation 1 = Inserts lane alignment characters |
1 | FRAME ALIGN | R/W | 0h | This bit inserts the lane alignment character (K28.7) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation 1 = Inserts frame alignment characters |
0 | TX LINK DIS | R/W | 0h | This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted.
0 = Normal operation 1 = ILA disabled |