SBAS706D April   2015  – April 2019 ADS54J60

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     FFT for 170-MHz Input Signal
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1 JESD Transmitter Interface
          2. 8.4.2.5.2 Eye Diagram
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
            1. Table 20. Register 0h Field Descriptions
          2. 8.5.2.1.2 Register 1h (address = 1h)
            1. Table 21. Register 1h Field Descriptions
          3. 8.5.2.1.3 Register 2h (address = 2h)
            1. Table 22. Register 2h Field Descriptions
          4. 8.5.2.1.4 Register 3h (address = 3h)
            1. Table 23. Register 3h Field Descriptions
          5. 8.5.2.1.5 Register 4h (address = 4h)
            1. Table 24. Register 4h Field Descriptions
          6. 8.5.2.1.6 Register 5h (address = 5h)
            1. Table 25. Register 5h Field Descriptions
          7. 8.5.2.1.7 Register 11h (address = 11h)
            1. Table 26. Register 11h Field Descriptions
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
            1. Table 27. Registers 20h Field Descriptions
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
            1. Table 28. Register 21h Field Descriptions
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
            1. Table 29. Register 23h Field Descriptions
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
            1. Table 30. Register 24h Field Descriptions
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
            1. Table 31. Register 26h Field Descriptions
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
            1. Table 32. Register 4Fh Field Descriptions
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
            1. Table 33. Register 53h Field Descriptions
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
            1. Table 34. Register 54h Field Descriptions
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
            1. Table 35. Register 55h Field Descriptions
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
            1. Table 36. Register 59h Field Descriptions
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (address = 5F), ADC Page (0Fh)
            1. Table 37. Register 5F Field Descriptions
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
            1. Table 38. Register 0h Field Descriptions
          2. 8.5.2.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
            1. Table 39. Register 41h Field Descriptions
          3. 8.5.2.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
            1. Table 41. Register 42h Field Descriptions
          4. 8.5.2.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
            1. Table 42. Register 43h Field Descriptions
          5. 8.5.2.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
            1. Table 43. Register 44h Field Descriptions
          6. 8.5.2.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
            1. Table 44. Register 4Bh Field Descriptions
          7. 8.5.2.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
            1. Table 45. Register 4Dh Field Descriptions
          8. 8.5.2.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
            1. Table 46. Register 4Eh Field Descriptions
          9. 8.5.2.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
            1. Table 47. Register 52h Field Descriptions
          10. 8.5.2.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
            1. Table 48. Register 72h Field Descriptions
          11. 8.5.2.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
            1. Table 49. Register ABh Field Descriptions
          12. 8.5.2.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
            1. Table 50. Register ADh Field Descriptions
          13. 8.5.2.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
            1. Table 51. Register F7h Field Descriptions
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
            1. Table 52. Register 0h Field Descriptions
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
            1. Table 53. Register 1h Field Descriptions
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
            1. Table 55. Register 2h Field Descriptions
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
            1. Table 56. Register 3h Field Descriptions
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
            1. Table 57. Register 5h Field Descriptions
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
            1. Table 58. Register 6h Field Descriptions
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
            1. Table 59. Register 7h Field Descriptions
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
            1. Table 60. Register 16h Field Descriptions
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
            1. Table 61. Register 31h Field Descriptions
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
            1. Table 62. Register 32h Field Descriptions
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
            1. Table 63. Register 12h-15h Field Descriptions
          2. 8.5.2.6.2 Registers 13h-15h (address = 13h-15h), JESD Analog Page (6A00h)
            1. Table 64. Register 13h-15h Field Descriptions
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
            1. Table 65. Register 16h Field Descriptions
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
            1. Table 66. Register 17h Field Descriptions
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
            1. Table 67. Register 1Ah Field Descriptions
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
            1. Table 68. Register 1Bh Field Descriptions
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
            1. Table 69. Register 068h Field Descriptions
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
            1. Table 70. Register 069h Field Descriptions
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
            1. Table 71. Registers 074h, 076h, 078h, 7Ah Field Descriptions
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
            1. Table 72. Registers 075h, 077h, 079h, 7Bh Field Descriptions
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
            1. Table 73. Registers 00h, 04h, 08h, 0Ch Field Descriptions
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
            1. Table 74. Registers 01h, 05h, 09h, 0Dh Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J60
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.1 Start-Up Sequence

The steps described in Table 75 are recommended as the power-up sequence with the ADS54J60 in 20X mode (LMFS = 8224).

Table 75. Initialization Sequence

STEP SEQUENCE DESCRIPTION PAGE BEING PROGRAMMED COMMENT
1 Power-up the device Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V. — See the Power Sequencing and Initialization section for power sequence requirements.
2 Reset the device Hardware reset
Apply a hardware reset by pulsing pin 48 (low → high → low). — A hardware reset clears all registers to their default values.
Register writes are equivalent to a hardware reset.
Write address 0-000h with 81h. General register Reset registers in the ADC and master pages of the analog bank.
This bit is a self-clearing bit.
Write address 4-001h with 00h and address 4-002h with 00h. Unused page Clear any unwanted content from the unused pages of the JESD bank.
Write address 4-003h with 00h and address 4-004h with 68h. — Select the main digital page of the JESD bank.
Write address 6-0F7h with 01h for channel A. Main digital page
(JESD bank)		 Use the DIG RESET register bit to reset all pages in the JESD bank.
This bit is a self-clearing bit.
Write address 6-000h with 01h, then address 6-000h with 00h. Pulse the PULSE RESET register bit for channel A.
3 Performance modes Write address 0-011h with 80h. — Select the master page of the analog bank.
Write address 0-059h with 20h. Master page
(analog bank)		 Set the ALWAYS WRITE 1 bit.
4 Program desired registers for
decimation options and
JESD link configuration 		Default register writes for DDC modes and JESD link configuration (LMFS 8224).
Write address 4-003h with 00h and address 4-004h with 69h. — Select the JESD digital page.
Write address 6-000h with 80h. JESD
digital page
(JESD bank)		 Set the CTRL K bit for both channels by programming K according to the SYSREF signal later on in the sequence.
JESD link is configured with LMFS = 8224 by default with no decimation. See Table 14 for configuring the JESD digital page registers for the desired LMFS and programming appropriate DDC mode.
Write address 4-003h with 00h and address 4-004h with 6Ah. — Select the JESD analog page.
JESD link is configured with LMFS = 8224 by default with no decimation. JESD
analog page
(JESD bank)		 See Table 14 for configuring the JESD analog page registers for the desired LMFS and programming appropriate DDC mode.
Write address 6-017h with 40h. PLL reset.
Write address 6-017h with 00h. PLL reset clear.
Write address 4-003h with 00h and address 4-004h with 68h. — Select the main digital page.
JESD link is configured with LMFS = 8224 by default with no decimation. Main digital page
(JESD bank)		 See Table 14 for configuring the main digital page registers for the desired LMFS and programming appropriate DDC mode.
Write address 6-000h with 01h and address 6-000h with 00h. Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed.
5 Set the value of K and the SYSREF signal frequency accordingly Write address 4-003h with 00h and address 4-004h with 69h. — Select the JESD digital page.
Write address 6-006h with XXh (choose the value of K). JESD
digital page
(JESD bank)		 See the SYSREF Signal section to choose the correct frequency for SYSREF.
6 JESD lane alignment Pull the SYNCB pin (pin 63) low. — Transmit K28.5 characters.
Pull the SYNCB pin high. After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data.