The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
ADS54J66 | VQFN (72) | 10.00 mm x 10.00 mm |
Changes from Revision A (December 2015) to Revision B (January 2023)
Changes from Revision * (November 2015) to Revision A (December 2015)
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
Input, Reference | |||
INAM | 41 | I | Differential analog input pins for channel A. Connect INAP to AVDD and INAM to GND if unused. |
INAP | 42 | ||
INBM | 37 | I | Differential analog input pins for channel B. Connect INBP to AVDD and INBM to GND if unused. |
INBP | 36 | ||
INCM | 18 | I | Differential analog input pins for channel C. Connect INCP to AVDD and INCM to GND if unused. |
INCP | 19 | ||
INDM | 14 | I | Differential analog input pins for channel D. Connect INDP to AVDD and INDM to GND if unused. |
INDP | 13 | ||
Clock, SYNC | |||
CLKINM | 28 | I | Differential clock input pins for the ADC |
CLKINP | 27 | ||
SYSREFM | 34 | I | External sync input pins |
SYSREFP | 33 | ||
Control, Serial | |||
DAM | 59 | O | JESD204B Serial data output pins for channel A. Connect a 100 Ohm resistor across DAM and DAP if unused. |
DAP | 58 | ||
DBM | 62 | O | JESD204B Serial data output pins for channel B. Connect a 100 Ohm resistor across DBM and DBP if unused. |
DBP | 61 | ||
DCM | 65 | O | JESD204B Serial data output pins for channel C. Connect a 100 Ohm resistor across DCM and DCP if unused. |
DCP | 66 | ||
DDM | 68 | O | JESD204B Serial data output pins for channel D. Connect a 100 Ohm resistor across DDM and DDP if unused. |
DDP | 69 | ||
NC | 1, 2, 22, 23, 53, 54 | – | Do not connect |
PDN | 50 | I/O | Power down. Can be configured via SPI register setting. |
RES | 49 | – | Reserve pin. Connect to GND |
RESET | 48 | I | Hardware reset. Active high. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 6 | I | Serial interface clock input |
SDIN | 5 | I | Serial interface data input. |
SDOUT | 11 | O | Serial interface data output. |
SEN | 7 | I | Serial interface enable |
SYNCbABM | 56 | I | Synchronization input pins for JESD204B port channel A, B. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination. |
SYNCbABP | 55 | ||
SYNCbCDM | 71 | I | Synchronization input pins for JESD204B port channel C, D. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination. |
SYNCbCDP | 72 | ||
Power Supply | |||
AGND | 21, 26, 29, 32 | I | Analog ground |
AVDD | 9, 12, 15, 17, 20, 25, 30, 35, 38, 40, 43, 44, 46 | I | Analog 1.9-V power supply |
AVDD3V | 10, 16, 24, 31, 39, 45 | I | Analog 3 V for analog buffer |
DGND | 3, 52, 60, 63, 67 | I | Digital ground |
DVDD | 8, 47 | I | Digital 1.9-V power supply |
IOVDD | 4, 51, 57, 64, 70 | I | Digital 1.15-V power supply for the JESD204B transmitter |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range | AVDD3V | –0.3 | 3.6 | V |
AVDD | –0.3 | 2.1 | ||
DVDD | –0.3 | 2.1 | ||
IOVDD | –0.2 | 1.4 | ||
Voltage between AGND and DGND | –0.3 | 0.3 | V | |
Voltage applied to input pins | INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM | –0.3 | 3 | V |
CLKINP, CLKINM | –0.3 | AVDD + 0.3 | ||
SYSREFP, SYSREFM | –0.3 | AVDD + 0.3 | ||
SCLK, SEN, SDIN, RESET, SPI_MODE, SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM, PDN | –0.2 | 2 | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Supply voltage range | AVDD3V | 2.85 | 3 | 3.6 | V | |
AVDD | 1.8 | 1.9 | 2 | |||
DVDD | 1.8 | 1.9 | 2 | |||
IOVDD | 1.1 | 1.15 | 1.2 | |||
Analog inputs | Differential input voltage range | 1.9 | VPP | |||
Input common-mode voltage | 2.0 ± 0.025 | V | ||||
Clock inputs | Input clock frequency, device clock frequency | 250 | 500 | MHz | ||
Input clock amplitude differential (VCLKP – VCLKM) | Sine wave, ac-coupled | 1.5 | VPP | |||
LVPECL, ac-coupled | 1.6 | |||||
LVDS, ac-coupled | 0.7 | |||||
Input device clock duty cycle, default after reset | 45% | 50% | 55% | |||
Temperature | Operating free-air, TA | –40 | 85 | °C | ||
Operating junction, TJ | 105(1) | 125 |
THERMAL METRIC(1) | ADS54J66 | UNIT | |
---|---|---|---|
RMP (VQFNP) | |||
72 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 22.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 5.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 2.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 2.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
General | |||||||
ADC sampling rate | 500 | MSPS | |||||
Resolution | 14 | Bits | |||||
Power Supply | |||||||
AVDD3V | 3-V analog supply | 2.85 | 3 | 3.6 | V | ||
AVDD | 1.9-V analog supply | 1.8 | 1.9 | 2 | V | ||
DVDD | 1.9-V digital supply | 1.8 | 1.9 | 2 | V | ||
IOVDD | 1.15-V SERDES supply | 1.1 | 1.15 | 1.2 | V | ||
IAVDD3V | 3-V analog supply current | 370-MHz, full-scale input on all four channels | 340 | mA | |||
IAVDD | 1.9-V analog supply current | 370-MHz, full-scale input on all four channels | 365 | mA | |||
IDVDD | 1.9-V digital supply current | 2x decimation (4 channels), 370 MHz, full-scale input on all four channels | 190 | mA | |||
DDC mode-8 (no decimation), 370 MHz, full-scale input on all four channels |
184 | ||||||
IIOVDD | 1.15-V SERDES supply current | DDC mode-8 (no decimation), 370 MHz, full-scale input on all four channels |
533 | mA | |||
Pdis | Total power dissipation | 2x decimation (4 channels), 370 MHz, full-scale input on all four channels | 2.68 | W | |||
DDC mode-8 (no decimation), 370 MHz, full-scale input on all four channels |
2.67 | ||||||
Global power-down power dissipation | Full-scale input on all four channels | 250 | mW | ||||
Analog Inputs | |||||||
Differential input full-scale voltage | 1.9 | VPP | |||||
Input common-mode voltage | 2.0 | V | |||||
Differential input resistance | At fIN = 370 MHz | 0.5 | kΩ | ||||
Differential input capacitance | At fIN = 370 MHz | 2.5 | pF | ||||
Analog input bandwidth (3 dB) | 900 | MHz | |||||
Isolation | |||||||
Crosstalk(1) isolation between near channels (channels A and B are near to each other, channels C and D are near to each other) |
fIN = 10 MHz | 105 | dBFS | ||||
fIN = 100 MHz | 104 | ||||||
fIN = 170 MHz | 96 | ||||||
fIN = 270 MHz | 97 | ||||||
fIN = 370 MHz | 93 | ||||||
fIN = 470 MHz | 85 | ||||||
Crosstalk(1) isolation between far channels (channels A and B, and channels C and D are far channels) |
fIN = 10 MHz | 110 | dBFS | ||||
fIN = 100 MHz | 107 | ||||||
fIN = 170 MHz | 96 | ||||||
fIN = 270 MHz | 97 | ||||||
fIN = 370 MHz | 95 | ||||||
fIN = 470 MHz | 94 | ||||||
Clock Input | |||||||
Internal clock biasing | CLKINP and CLKINM pins are connected to internal biasing voltage through 400 Ω | 1.15 | V |
PARAMETER | TEST CONDITIONS | NO DECIMATION, 500-MSPS OUTPUT (DDC Mode 8) | DECIMATE-BY-2, 250-MSPS OUTPUT (DDC Mode 2) | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 70.8 | 74.1 | dBFS | ||||
fIN = 70 MHz | 70.5 | 74 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 69.5 | 73.2 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 65.6 | 70.3 | 73.6 | ||||||
fIN = 300 MHz | 69 | 72.6 | |||||||
fIN = 350 MHz | 68.7 | 72 | |||||||
fIN = 370 MHz | 64.6 | 68.4 | 71.5 | ||||||
fIN = 470 MHz | 67.5 | 70.7 | |||||||
NSD | Noise spectral density | fIN = 10 MHz | 154.8 | 155.1 | dBFS/Hz | ||||
fIN = 70 MHz | 154.5 | 155 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 153.5 | 154.2 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 149.6 | 154.3 | 154.6 | ||||||
fIN = 300 MHz | 153 | 153.6 | |||||||
fIN = 350 MHz | 152.7 | 153 | |||||||
fIN = 370 MHz | 148.6 | 152.4 | 152.5 | ||||||
fIN = 470 MHz | 151.5 | 151.7 | |||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.7 | 73.9 | dBFS | ||||
fIN = 70 MHz | 70.4 | 73.9 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 69.4 | 73.1 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 70.2 | 73.5 | |||||||
fIN = 300 MHz | 68.9 | 72.5 | |||||||
fIN = 350 MHz | 68.6 | 71.7 | |||||||
fIN = 370 MHz | 68.2 | ||||||||
fIN = 470 MHz | 66.9 | 69.7 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 89 | 88 | dBc | ||||
fIN = 70 MHz | 87 | 95 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 86 | 97 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 78 | 88 | 96 | ||||||
fIN = 300 MHz | 82 | 94 | |||||||
fIN = 350 MHz | 82 | 82 | |||||||
fIN = 370 MHz | 75 | 81 | |||||||
fIN = 470 MHz | 73 | 74 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 89 | 91 | dBc | ||||
fIN = 70 MHz | 94 | 103 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 86 | 101 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 78 | 88 | 101 | ||||||
fIN = 300 MHz | 82 | 97 | |||||||
fIN = 350 MHz | 82 | 82 | |||||||
fIN = 370 MHz | 75 | 81 | |||||||
fIN = 470 MHz | 73 | 74 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 93 | 88 | dBc | ||||
fIN = 70 MHz | 87 | 99 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 98 | 100 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 78 | 97 | 98 | ||||||
fIN = 300 MHz | 95 | 100 | |||||||
fIN = 350 MHz | 90 | 96 | |||||||
fIN = 370 MHz | 75 | 85 | |||||||
fIN = 470 MHz | 83 | 83 | |||||||
Non HD2, HD3 | Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 94 | 98 | dBc | ||||
fIN = 70 MHz | 94 | 95 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 93 | 97 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 87 | 93 | 96 | ||||||
fIN = 300 MHz | 92 | 94 | |||||||
fIN = 350 MHz | 91 | 94 | |||||||
fIN = 370 MHz | 80 | 90 | |||||||
fIN = 470 MHz | 87 | 93 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 88 | 86 | dBc | ||||
fIN = 70 MHz | 85 | 92 | |||||||
fIN = 190 MHz, AIN = –1 dBFS | 85 | 92 | |||||||
fIN = 190 MHz, AIN = –3 dBFS | 86 | 91 | |||||||
fIN = 300 MHz | 81 | 89 | |||||||
fIN = 350 MHz | 79 | 82 | |||||||
fIN = 370 MHz | 78 | ||||||||
fIN = 470 MHz | 72 | 73 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN = 185 MHz, fIN = 190 MHz, AIN = –7 dBFS | 89 | dBFS | |||||
fIN = 365 MHz, fIN = 370 MHz, AIN = –7 dBFS | 82 | ||||||||
fIN = 465 MHz, fIN = 470 MHz, AIN = –7 dBFS | 77 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Digital Inputs (RESET, SCLK, SEN, SDIN, PDN)(1) | ||||||
VIH | High-level input voltage | All digital inputs support 1.2-V and 1.8-V logic levels | 0.8 | V | ||
VIL | Low-level input voltage | All digital inputs support 1.2-V and 1.8-V logic levels | 0.4 | V | ||
IIH | High-level input current | SEN | 0 | µA | ||
RESET, SCLK, SDIN, PDN | 100 | |||||
IIL | Low-level input current | SEN | 50 | µA | ||
RESET, SCLK, SDIN, PDN | 0 | |||||
Digital Inputs (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP) | ||||||
VD | Differential input voltage | 0.35 | 0.45 | 1.4 | V | |
V(CM_DIG) | Common-mode voltage for SYSREF | 1.3 | V | |||
Digital Outputs (SDOUT, PDN) | ||||||
VOH | High-level output voltage | DVDD – 0.1 | DVDD | V | ||
VOL | Low-level output voltage | 0.1 | V | |||
Digital Outputs (JESD204B Interface: DxP, DxM)(2) | ||||||
VOD | Output differential voltage | With default swing setting | 700 | mVPP | ||
VOC | Output common-mode voltage | 450 | mV | |||
Transmitter short-circuit current | Transmitter pins shorted to any voltage between –0.25 V and 1.45 V | –100 | 100 | mA | ||
zos | Single-ended output impedance | 50 | Ω | |||
Output capacitance | Output capacitance inside the device, from either output to ground | 2 | pF |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
Sample Timing Characteristics (TBD are any of these Switching Characteristics?) | ||||||
Aperture delay | 0.75 | 1.6 | ns | |||
Aperture delay matching between two channels on the same device | ±70 | ps | ||||
Aperture delay matching between two devices at the same temperature and supply voltage | ±270 | ps | ||||
Aperture jitter | 135 | fS rms | ||||
Wake-up time to valid data after coming out of global power-down | 150 | µs | ||||
Data latency(1): ADC sample to digital output | 77 | Input clock cycles | ||||
OVR latency: ADC sample to OVR bit | 44 | Input clock cycles | ||||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over | 4 | ns | |||
tSU_SYSREF(2) | Setup time for SYSREF, referenced to input clock falling edge | 300 | ps | |||
tH_SYSREF(2) | Hold time for SYSREF, referenced to input clock falling edge | 100 | ps | |||
JESD Output Interface Timing Characteristics | ||||||
Unit interval | 100 | 400 | ps | |||
Serial output data rate | 2.5 | 10 | Gbps | |||
Total jitter for BER of 1E-15 and lane rate = 10 Gbps | 26 | ps | ||||
Random jitter for BER of 1E-15 and lane rate = 10 Gbps | 0.75 | ps rms | ||||
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps | 12 | ps, pk-pk | ||||
tR, tF | Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps | 35 | ps |
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
fIN = 10 MHz , AIN = –1 dBFS, SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (non 23) |
fIN = 190 MHz , AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23) |
fIN = 300 MHz , AIN = –3 dBFS, SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (non 23) |
fIN = 470 MHz , AIN = –3 dBFS, SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (non 23) |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 103 dBFS, each tone at –36 dBFS |
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 102 dBFS, each tone at –36 dBFS |
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 98.8 dBFS, each tone at –36 dBFS |
fIN1 = 365 MHz, fIN2 = 370 MHz |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 370 MHz |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 370 MHz, AIN = –3 dBFS | ||
fIN = 190 MHz, AIN = –1 dBFS | ||
fIN = 190 MHz, AIN= –1 dBFS 50-mVPP test signal on input common-mode |
fIN = 140 MHz , AIN = –1 dBFS, SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (non 23) |
fIN = 230 MHz , AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23) |
fIN = 370 MHz , AIN = –3 dBFS, SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (non 23) |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 89 dBFS, each tone at –7 dBFS |
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 81.7 dBFS, each tone at –7 dBFS |
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 76.7 dBFS, each tone at –7 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz | ||
fIN1 = 465 MHz, fIN2 = 470 MHz |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 370 MHz, AIN = –3 dBFS |
fIN = 190 MHz |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 190 MHz, AIN = –1 dBFS |
fIN = 190 MHz , AIN = –1 dBFS SFDR = 49 dBc, fPSRR = 5 MHz, APSRR = 50 mVPP |
fIN = 190 MHz , AIN = –1 dBFS SFDR = 81 , fCMRR = 5 MHz, ACMRR = 50 mVPP |
low-pass or high-pass decimation-by-2 filter selected as per input frequency; typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
fIN = 100 MHz, AIN = –1 dBFS, SNR = 74.1 dBFS, SFDR = 98 dBc, SFDR = 100 dBc (non 23) |
fIN = 185 MHz, AIN = – 1 dBFS, SNR = 73.2 dBFS, SFDR = 98 dBc, SFDR = 98 dBc (non 23) |
fIN = 150 MHz, AIN = –1 dBFS, SNR = 73.8 dBFS, SFDR = 99 dBc, SFDR = 99 dBc (non 23) |
fIN = 230 MHz, AIN = –1 dBFS, SNR = 72.4 dBFS, SFDR = 91 dBc, SFDR = 98 dBc (non 23) |
low-pass decimation-by-2 filter selected, complex FFT plotted, mixer frequency 125 MHz; typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
fIN = 270 MHz, AIN = –3 dBFS, SNR = 69.5 dBFS, SFDR = 83 dBc, SFDR = 87 dBc (non 23) |
fIN = 470 MHz, AIN = –3 dBFS, SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (non 23) |
fIN = 370 MHz, AIN = –3 dBFS, SNR = 68.1 dBFS, SFDR = 82 dBc, SFDR = 82 dBc (non 23) |
The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports the JESD204B serial interface with data rates up to 10 Gbps supporting one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The device digital block includes a 2x and 4x decimation low-pass filter with fS / 4 and k × fS / 16 mixers to support a receive bandwidth up to 200 MHz for use as a Digital Pre-Distortion (DPD) observation receiver.
The JESD204B interface reduces the number of interface lines allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used to serialize the 14-bit data from each channel.
The ADS54J66 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows for ac coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.
In order to achieve optimum ac performance the circuitry shown in Figure 7-1 is recommended at the analog inputs.
The ADS54J66 supports decimation-by-2 and -4 and un-decimated output. The four channels can be configured as pairs (A, B and C, D; however, the same decimation factor must be chosen for all four channels).
Figure 7-2 shows signal processing done in the digital down-conversion (DDC) block of the ADS54J66. Table 7-1 shows available modes of operation for this block.
OPERATING MODE | DESCRIPTION | DIGITAL MIXER | DECIMATION | BANDWIDTH | OUTPUT FORMAT | MAX OUTPUT RATE | |
---|---|---|---|---|---|---|---|
491 MSPS | 368 MSPS | ||||||
0 | Decimation | ±fS / 4 | 2 | 200 MHz | 150 MHz | Complex | 250 MSPS |
2 | – | 2 | 100 MHz | 75 MHz | Real | 250 MSPS | |
4 | N × fS / 16 | 2 | 100 MHz | 75 MHz | Real | 250 MSPS | |
5 | N × fS / 16 | 2 | 200 MHz | 150 MHz | Complex | 250 MSPS | |
6 | N × fS / 16 | 4 | 100 MHz | 75 MHz | Complex | 125 MSPS | |
7 | N × fS / 16 | 2 | 100 MHz | 75 MHz | Real | 500 MSPS | |
8 | No decimation | – | – | 245.76 MHz | 184.32 MHz | Real | 500 MSPS |
Table 7-2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.
MODE | fmix1 | FILTER AND DECIMATION | fmix2 | OUTPUT |
---|---|---|---|---|
0 | fS / 4 | LPF cutoff at fS / 4, decimation-by-2 | Not used | I, Q data at 250 MSPS each are given out |
2 | Not used | LPF or HPF cutoff at fS / 4, decimation-by-2 | Not used | Straight 250 MSPS data are given out |
4 | k fS / 16 | LPF cutoff at fS / 8, decimation-by-2 | fS / 8 | Real data at 250 MSPS are given out |
5 | k fS / 16 | LPF cutoff at fS / 8, decimation-by-2 | Not used | I, Q data at 250 MSPS each are given out |
6 | k fS / 16 | LPF cutoff at fS / 8, decimation-by-4 | Not used | I, Q data at 125 MSPS each are given out |
7 | k fS / 16 | LPF cutoff at fS8, decimation-by-2 | fS / 8 | Real data are up-scaled, zero-padded and given out at 500 MSPS |
Default | Not used | Not used | Not used | Straight 500-MSPS, 14-bit data are given out |
In this configuration, the DDC block includes a fixed frequency ±fS / 4 complex digital mixer preceding the digital filter, so the IQ passband is approximately ±110 MHz (3 dB) centered at fS / 4. Mixing with +fS / 4 inverts the spectrum. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.1 dB. Figure 7-3 shows mixing operation in DDC mode 0. Table 7-3 shows corner frequencies of decimation filter in DDC mode 0. Figure 7-4 and Figure 7-5 show frequency response of the filter.
CORNERS | LOW PASS |
---|---|
–0.1 dB | 0.204 × fS |
–0.5 dB | 0.211 × fS |
–1 dB | 0.216 × fS |
–3 dB | 0.226 × fS |
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7) preceding the decimation-by-2 digital filter also with an IQ passband of approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum. In addition, a fS / 8 complex digital mixer is added after the decimation filter transforming the output back to real format and centers the output spectrum within the Nyquist zone.
In addition, the ADS54J66 supports a 0-pad feature where a sample with value = 0 is added after each sample. In this way the output data rate is interpolated to 500 MSPS (real) with a second image inverted at fS / 2 – fIN.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and approximately 55 dB for out-of-band aliases. The passband flatness is ±0.1 dB. Figure 7-9 shows the filtering operation in DDC mode 4 and 7. Table 7-5 shows corner frequencies of decimation filter in DDC mode 4 and 7. Figure 7-10 and Figure 7-11 show frequency response of the filter.
CORNERS | LOW PASS |
---|---|
–0.1 dB | 0.102 × fS |
–0.5 dB | 0.105 × fS |
–1 dB | 0.108 × fS |
–3 dB | 0.113 × fS |
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7) preceding the decimation-by-2 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The pass-band flatness is ±0.1 dB. Figure 62 shows the filtering operation in DDC mode 5. Table 6 shows corner frequencies of decimation filter in DDC mode 5. Figure 63 and Figure 64 show frequency response of the filter. Figure 7-12 shows the filtering operation in DDC mode 5. Table 7-6 shows corner frequencies of decimation filter in DDC mode 5. Figure 7-13 and Figure 7-14 show frequency response of the filter.
CORNERS | LOW PASS |
---|---|
–0.1 dB | 0.102 × fS |
–0.5 dB | 0.105 × fS |
–1 dB | 0.108 × fS |
–3 dB | 0.113 × fS |
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (n from –8 to +7) preceding the decimation-by-4 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum. Figure 7-15 shows the filtering operation in DDC mode 6. Table 7-7 shows corner frequencies of decimation filter in DDC mode 6. The decimation-by-4 filter is a cascade of two decimation-by-2 filters with frequency response shown in Figure 7-16 and Figure 7-17.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and approximately 55 dB for out-of-band aliases. The pass-band flatness is ±0.1 dB.
CORNERS | LOW PASS |
---|---|
–0.1 dB | 0.102 × fS |
–0.5 dB | 0.105 × fS |
–1 dB | 0.108 × fS |
–3 dB | 0.113 × fS |
The ADS54J66 provides a fast overrange indication (FOVR) that can be presented in the digital output data stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the LSB (normal 0) of the 16 bit going to the 8b/10b encoder as shown in Figure 7-18.
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.
The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using the FOVR THRESHOLD bits.
These register bits set the OVR threshold for all channels.
The input voltage level that fast OVR is triggered is:
Full-scale × [the decimal value of the FOVR threshold bits] / 255)
The default threshold is E3h (227), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as shown in Equation 1:
Table 7-8 is an example register write to set the FOVR threshold for all four channels.
ADDRESS | DATA | COMMENT |
---|---|---|
11h | 80h | Go to master page |
59h | 20h | Set the ALWAYS WRITE 1 bit. This bit configures the OVR signal as fast OVR. |
11h | 0Fh | Go to ADC page |
5Fh | FFh | Set FOVR threshold for all channels to 255 |
4004h | 68h | Go to main digital page of the JESD bank |
4003h | 00h | |
60ABh | 01h | Enable bit D0 overwrite |
70ABh | 01h | |
60ADh | 03h | Select FOVR to replace bit D0 |
70ADh | 03h | |
6000h | 01h | Pulse the IL RESET register bit. Register writes in main digital page take effect when the IL RESET register bit is pulsed. |
7000h | 01h | |
6000h | 00h | |
7000h | 00h |
The ADS54J66 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 7-9. See the master page registers in Table 7-15 for further details.
REGISTER ADDRESS A[7:0] (Hex) | COMMENT | REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
MASTER PAGE (80h) | |||||||||
20 | MASK 1 | PDN ADC CHAB | PDN ADC CHCD | ||||||
21 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | |||
23 | MASK 2 | PDN ADC CHAB | PDN ADC CHCD | ||||||
24 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | |||
26 | CONFIG | GLOBAL PDN | OVERRIDE PDN PIN | PDN MASK SEL | 0 | 0 | 0 | 0 | 0 |
53 | 0 | MASK SYSREF | 0 | 0 | 0 | 0 | 0 | 0 | |
55 | 0 | 0 | 0 | PDN MASK | 0 | 0 | 0 | 0 |
To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However, when JESD link must remain up when putting the device in power down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 7-10 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits.
REGISTER BIT | COMMENT | IAVDD3V (mA) | IAVDD (mA) | IDVDD (mA) | IIOVDD (mA) | TOTAL POWER (W) |
---|---|---|---|---|---|---|
Default | After reset, with a full-scale input signal to both channels | 0.340 | 0.365 | 0.184 | 0.533 | 2.675 |
GBL PDN = 1 | The device is in complete power-down state | 0.002 | 0.006 | 0.012 | 0.181 | 0.247 |
GBL PDN = 0, PDN ADC CHx = 1 (x = AB or CD) | The ADCs of one pair of channels are powered down | 0.277 | 0.225 | 0.123 | 0.496 | 2.063 |
GBL PDN = 0, PDN BUFF CHx = 1 (x = AB or CD) | The input buffers of one pair of channels are powered down | 0.266 | 0.361 | 0.187 | 0.527 | 2.445 |
GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = AB or CD) | The ADCs and input buffers of one pair of channels are powered down | 0.200 | 0.224 | 0.126 | 0.492 | 1.830 |
GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = AB and CD) | The ADCs and input buffers of all channels are powered down | 0.060 | 0.080 | 0.060 | 0.448 | 0.960 |
The ADS54J66 can be configured using a serial programming interface, as described in this section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS54J66 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Section 7.6.1 section) to access all register bits. Figure 7-19 shows timing diagram for serial interface signals. SPI registers are grouped in two banks with each bank containing different pages (see Figure 7-34).
First 4 MSBs of 16-bit address are special bits carrying information about register bank, page and channel to be programmed. Table 7-11 lists the purpose of each special bit.
SPI BITS | DESCRIPTION | OPTIONS |
---|---|---|
R/W | Read/write bit | 0 = SPI write 1 = SPI read back |
M | SPI bank access | 0 = Analog SPI bank (master and ADC page) 1 = Digital SPI bank (main digital, analog JESD, and digital JESD pages) |
P | JESD page selection bit | 0 = Page access 1 = Register access |
CH | SPI access for a specific channel of the digital SPI bank | 0 = Channel AB 1 = Channel CD By default, both channels are being addressed. |
ADDR [11:0] | SPI address bits | — |
DATA [7:0] | SPI data bits | — |
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 5 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
Figure 7-24 shows timing requirements for serial interface signals.
MIN | MAX | UNIT | ||
---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz |
tSLOADS | SEN to SCLK setup time | 25 | ns | |
tSLOADH | SCLK to SEN hold time | 25 | ns | |
tDSU | SDATA setup time | 25 | ns | |
tDH | SDATA hold time | 25 | ns |
The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J66 analog SPI bank can be programmed by:
The content from one of the two analog banks can be read out by:
The JESD SPI bank contains five pages (main digital, interleaving engine, decimation filter, JESD digital, and JESD analog). The individual pages can be selected following these steps:
Figure 7-22 shows the serial interface signals when pages in the JESD bank are being accessed. Note that the P bit is set to 0.
The ADS54J66 is a quad-channel device and the JESD204B portion is configured individually for two channels (A, B and C, D) using the CH bit. Note that the P bit must be set to 1 for register writes.
Figure 7-23 shows the serial interface signals when a register in the desired page of the JESD bank is programmed (note that the P bit must be set to 1 in this step).
By default, register writes are applied to both channels in a group (for example, the register writes are applied to channels A and B if the CH bit is 0, or the register writes are applied to channels C and D if the CH bit is 1). This form of programming is referred to as broadcast mode.
For pages located in the JESD bank, the device gives flexibility to program each channel individually. To enable individual channel writes, write address 4005h with 01h (default is 00h).
SPI read out of content in one of the three digital banks can be accomplished with the following steps:
Figure 7-24 shows the serial interface signals when the contents of a register in the desired page of the JESD bank are being read-back (note that the P bit must be set to 1 in this step).
The ADS54J66 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial transmitter. Figure 7-25 shows JESD20B block inside ADS54J66.
An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. The ADS54J66 supports single (for all four JESD links) or dual (for channel A, B and C, D) SYNCb inputs and can be configured via SPI as shown in Figure 7-26.
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one lane per channel. The JESD204B setup and configuration of the frame assembly parameters is controlled through the SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled.
The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon detecting a logic low on the SYNC input pins, the ADS54J66 starts transmitting comma (K28.5) characters to establish code group synchronization as shown in Figure 7-27.
When synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS54J66 starts the initial lane alignment sequence with the next local multi frame clock boundary. The ADS54J66 transmits four multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
The JESD204B standard defines the following parameters:
Table 7-13 lists the available JESD204B formats and valid ranges for the ADS54J66. The ranges are limited by the Serdes line rate and the maximum ADC sample frequency.
L | M | F | S | OPERATING MODE | DIGITAL MODE | OUTPUT FORMAT | JESD MODE(1) | JESD PLL MODE(2) | MAX ADC OUTPUT RATE (MSPS) | MAX fSERDES (Gbps) |
---|---|---|---|---|---|---|---|---|---|---|
4 | 8 | 4 | 1 | 0,5 | 2x decimation | Complex | 40x | 40x | 250 | 10.0 |
4 | 4 | 2 | 1 | 2,4 | 2x decimation | Real | 20x | 20x | 250 | 5.0 |
2 | 4 | 4 | 1 | 2,4 | 2x decimation | Real | 40x | 40x | 250 | 10.0 |
4 | 8 | 4 | 1 | 6 | 4x decimation | Complex | 40x | 20x | 125 | 5.0 |
4 | 4 | 2 | 1 | 7 | 2x decimation with 0-pad | Real | 20x | 40x | 500 | 10.0 |
4 | 4 | 2 | 1 | 8 | No decimation | Real | 20x | 40x | 500 | 10.0 |
The detailed frame assembly is shown in Table 7-14.
LMFS = 4841 | LMFS = 4421 | LMFS = 4421 (0-Pad) | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DA | AI0[15:8] | AI0[7:0] | AQ0[15:8] | AQ0[7:0] | A0[15:8] | A0[7:0] | A1[15:8] | A1[7:0] | A0[15:8] | A0[7:0] | 0000 0000 | 0000 0000 | ||
DB | BI0[15:8] | BI0[7:0] | BQ0[15:8] | BQ0[7:0] | B0[15:8] | B0[7:0] | B1[15:8] | B1[7:0] | B0[15:8] | B0[7:0] | 0000 0000 | 0000 0000 | ||
DC | CI0[15:8] | CI0[7:0] | CQ0[15:8] | CQ0[7:0] | C0[15:8] | C0[7:0] | C1[15:8] | C1[7:0] | C0[15:8] | C0[7:0] | 0000 0000 | 0000 0000 | ||
DD | DI0[15:8] | DI0[7:0] | DQ0[15:8] | DQ0[7:0] | D0[15:8] | D0[7:0] | D1[15:8] | D1[7:0] | D0[15:8] | D0[7:0] | 0000 0000 | 0000 0000 |
LMFS = 2441 | ||||
DB | A0[15:8] | A0[7:0] | B0[15:8] | B0[7:0] |
DC | C0[15:8] | C0[7:0] | D0[15:8] | D0[7:0] |
The ADS54J66 provides a digital cross point switch in the JESD204B block which allows internal routing of any output of the two ADCs within one channel pair to any of the two JESD204B serial transmitters in order to ease layout constraints. The cross-point switch routing is configured via SPI (address 21h in the JESD digital page, as shown in Figure 7-28).
Each of the 10 Gbps serdes transmitter outputs requires ac coupling between transmitter and receiver. The differential pair must be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted reflections and signal degradation as shown in Figure 7-29.
The ADS54J66 supports single (either SYNCb input controls all four JESD204B links) or dual (one SYNCb input controls two JESD204B lanes (DA, DB and DC, DD) SYNCb control. When using single SYNCb control, connect the unused input to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).
Figure 7-30 to Figure 7-33 show the serial output eye diagrams of the ADS54J66 at 5 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask.
The conceptual diagram of the serial registers is shown in Figure 7-34.
The ADS54J66 contains two main SPI banks. The analog SPI bank gives access to the ADC cores and the digital SPI bank controls the serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into five pages (main digital, interleaving engine, decimation filter, JESD digital, and JESD analog; see Figure 7-34). Table 7-15 gives a summary of all programmable registers in the pages of different banks in the ADS54J66.
REGISTER
ADDRESS A[7:0] (Hex) |
REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
GENERAL REGISTERS | ||||||||
0 | RESET | 0 | 0 | 0 | 0 | 0 | 0 | RESET |
3 | JESD BANK PAGE SEL [7:0] | |||||||
4 | JESD BANK PAGE SEL [15:8] | |||||||
5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIS BROADCAST |
11 | ANALOG PAGE SELECTION [7:0] | |||||||
MASTER PAGE (80h) | ||||||||
20 | PDN ADC CHAB | PDN ADC CHCD | ||||||
21 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | ||
23 | PDN ADC CHAB | PDN ADC CHCD | ||||||
24 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | ||
26 | GLOBAL PDN | OVERRIDE PDN PIN | PDN MASK SEL | 0 | 0 | 0 | 0 | 0 |
3A | 0 | BUFFER CURR INCREASE | 0 | 0 | 0 | 0 | 0 | 0 |
39 | ALWAYS WRITE 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
53 | CLK DIV | MASK SYSREF | 0 | 0 | 0 | 0 | 0 | SET SYSREF |
54 | ENABLE MANUAL SYSREF | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
55 | 0 | 0 | 0 | PDN MASK | 0 | 0 | 0 | 0 |
56 | 0 | 0 | 0 | 0 | INPUT BUFF CURR EN | 0 | 0 | 0 |
59 | 0 | 0 | ALWAYS WRITE 1 | 0 | 0 | 0 | 0 | 0 |
ADC PAGE (0Fh) | ||||||||
5F | FOVR THRESH | |||||||
60 | PULSE BIT CHC | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
61 | 0 | 0 | 0 | 0 | HD3 NYQ2 CHCD | 0 | 0 | PULSE BIT CHD |
6C | PULSE BIT CHA | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
6D | 0 | 0 | 0 | 0 | HD3 NYQ2 CHAB | 0 | 0 | PULSE BIT CHB |
74 | TEST PATTERN ON CHANNEL | 0 | 0 | 0 | 0 | |||
75 | CUSTOM PATTERN 1 [13:6] | |||||||
76 | CUSTOM PATTERN 1 [5:0] | 0 | 0 | |||||
77 | CUSTOM PATTERN 2 [13:6] | |||||||
78 | CUSTOM PATTERN 2 [5:0] | 0 | 0 | |||||
INTERLEAVING ENGINE PAGE (6100h) | ||||||||
18 | 0 | 0 | 0 | 0 | 0 | 0 | IL BYPASS | |
68 | 0 | 0 | 0 | 0 | 0 | DC CORR DIS | 0 | |
DECIMATION FILTER PAGE (6141h) | ||||||||
0 | CHB/C FINE MIX | DDC MODE | ||||||
1 | 0 | 0 | 0 | 0 | DDC MODE6 EN1 | ALWAYS WRITE 1 | CHB/C HPF EN | CHB/C COARSE MIX |
2 | 0 | 0 | CHA/D HPF EN | CHA/D COARSE MIX | CHA/D FINE MIX | |||
MAIN DIGITAL PAGE (6800h) | ||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IL RESET |
42 | 0 | 0 | 0 | 0 | 0 | NYQUIST ZONE | ||
4E | CTRL NYQUIST ZONE | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
AB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OVR EN |
F7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIG RESET |
JESD DIGITAL PAGE (6900h) | ||||||||
0 | CTRL K | JESD MODE EN | DDC MODE6 EN2 | TESTMODE EN | 0 | LANE ALIGN | FRAME ALIGN | TX LINK DIS |
1 | SYNC REG | SYNC REG EN | SYNCB SEL AB/CD | 0 | DDC MODE6 EN3 | 0 | JESD MODE | |
2 | LINK LAYER TESTMODE | LINK LAYER RPAT | LMFC MASK RESET | 0 | 0 | 0 | ||
3 | FORCE LMFC COUNT | LMFC COUNT INIT | RELEASE ILANE SEQ | |||||
5 | SCRAMBLE EN | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
6 | 0 | 0 | 0 | FRAMES PER MULTI FRAME (K) | ||||
21 | OUPUT CHA MUX SEL | OUTPUT CHB MUX SEL | OUTPUT CHC MUX SEL | OUTPUT CHD MUX SEL | ||||
22 | 0 | 0 | 0 | 0 | OUT CHA INV | OUT CHB INV | OUT CHC INV | OUT CHD INV |
JESD ANALOG PAGE (6A00h) | ||||||||
12 | SEL EMP LANE A/D | 0 | 0 | |||||
13 | SEL EMP LANE B/C | 0 | 0 | |||||
16 | 0 | 0 | 0 | 0 | 0 | 0 | JESD PLL MODE | |
17 | 0 | PLL RESET | 0 | 0 | 0 | 0 | 0 | 0 |
1B | JESD SWING | 0 | 0 | 0 | 0 | 0 |
Global power down:
ADDRESS | DATA | COMMENT |
---|---|---|
11h | 80h | Set master page |
0026h | C0h | Set global power down |
Change decimation mode 0 to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as well as serial output data rate (10 Gbps to 5 Gbps):
ADDRESS | DATA | COMMENT |
---|---|---|
4004h | 69h | Select digital JESD page |
4003h | 00h | |
6000h | 40h | Enables JESD mode overwrite |
6001h | 01h | Select digital to 20x mode |
4004h | 6Ah | Select analog JESD page |
6016h | 00h | Set serdes PLL to 20x mode |
4004h | 61h | Select decimation filter page |
4003h | 41h | |
6000h | CCh | Select mode 4 Digital mixer for channel AB set to –4 (fS / 4) |
6002h | 0Ch | Digital mixer for channel CD set to –4 (fS / 4) |
Table 7-16 lists the access codes for the ADS54J66 registers.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RW | R-W | Read or write |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | RESET |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7(1) | RESET | R/W | 0h | 0 = Normal operation 1 = Internal software reset, clears back to 0 |
6-0 | 0 | W | 0h | Must write 0. |
0(1) | RESET | R/W | 0h | 0 = Normal operation 1 = Internal software reset, clears back to 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD BANK PAGE SEL [7:0] | |||||||
R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD BANK PAGE SEL [16:8] | |||||||
R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-0 | JESD BANK PAGE SEL | R/W | 0h | Program these bits to access the desired page in the JESD bank. 6100h = Interleaving engine page selected 6141h = Decimation filter page selected 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | DIS BROADCAST |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | DIS BROADCAST | R/W | 0h | 0 = Normal operation. Channel A and B are programmed as a pair. Channel C and D are programmed as a pair. 1 = channel A and B can be individually programmed based on the CH bit. Similarly channel C and D can be individually programmed based on the CH bit. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ANALOG PAGE SELECTION [7:0] | |||||||
R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-0 | ANALOG PAGE SELECTION [7:0] | R/W | 0h | Register page (only one page at a time can be addressed). Master page = 80h ADC page = 0Fh The five digital pages (main digital, interleaving engine, analog JESD, digital JESD, and decimation filter) are selected via the M bit. See Table 7-11 in the Section 7.5.1.1 section for more details. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | BUFFER CURR INCREASE | 0 | 0 | 0 | 0 | 0 | 0 |
W-0h | R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | W | 0h | Must write 0. |
6 | BUFFER CURR INCREASE | R/W | 0h | 0 = Normal operation 1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second and third Nyquist application. Make sure that the INPUT BUF CUR EN regiser bit is also set to 1. |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALWAYS WRITE 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-6 | ALWAYS WRITE 1 | R/W | 0h | Always set these bits to 11. |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK DIV | MASK SYSREF | 0 | 0 | 0 | 0 | 0 | SET SYSREF |
R/W-0h | R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7 | CLK DIV | R/W | 0h | This bit configures the input clock divider. 0 = Divide-by-4 1 = Divide-by-2 (must be enabled for proper operation of the ADS54J66) |
6 | MASK SYSREF | R/W | 0h | 0 = Normal operation 1 = Ignores the SYSREF input |
5-1 | 0 | W | 0h | Must write 0. |
0 | SET SYSREF | R/W | 0h | 0 = SYSREF signal inside device is set as 0 1 = SYSREF signal inside device is set as 1 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE MANUAL SYSREF | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7 | ENABLE MANUAL SYSREF | R/W | 0h | This bit enables manual SYSREF using SPI when disabling the pin control. After setting this bit, the SET SYSREF register bit can be used to apply SYSREF. |
6-1 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | PDN MASK | 0 | 0 | 0 | 0 |
W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-5 | 0 | W | 0h | Must write 0. |
4 | PDN MASK | R/W | 0h | Power-down via register bit. 0 = Normal operation 1 = Power down enabled powering down internal blocks specified in the selected power-down mask |
3-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | INPUT BUFF CURR EN | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | INPUT BUFF CURR EN | R/W | 0h | 0 = Normal operation 1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second Nyquist application. Make sure that the BUFFER CURR INCREASE register bit is also set to 1. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | ALWAYS WRITE 1 | 0 | 0 | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | ALWAYS WRITE 1 | R/W | 0h | Always set this bit to 1. |
4-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FOVR THRESH | |||||||
R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-0 | FOVR THRESH | R/W | 0h | These bits control the location of FAST OVR threshold for all four channels together; see the Section 7.4.7 section. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PULSE BIT CHC | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7 | PULSE BIT CHC | R/W | 0h | Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel C.(1) Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1. |
6-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | HD3 NYQ2 CHCD | 0 | 0 | PULSE BIT CHD |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | R/W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | HD3 NYQ2 CHCD | R/W | 0h | Set this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel C and D. When this bit is set, the PULSE BIT CHx register bits must be pulsed to obtain the improvement in corresponding channels. |
2-1 | 0 | W | 0h | Must write 0. |
0 | PULSE BIT CHD | R/W | 0h | Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel D.(1) Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PULSE BIT CHA | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
7 | PULSE BIT CHA | R/W | 0h | Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel A.(1) Before pulsing this bit, the HD3 NYQ2 CHCAB register bit must be set to 1. |
6-0 | 0 | W | 0h | Must write 0. |