SBAS745B December   2015  – January 2023 ADS54J66

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics: General (DDC Mode-8)
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
      2. 7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7 Overrange Indication
      8. 7.4.8 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1 Details of the Serial Interface
        2. 7.5.1.2 Serial Register Write: Analog Bank
        3. 7.5.1.3 Serial Register Readout: Analog Bank
        4. 7.5.1.4 JESD Bank SPI Page Selection
        5. 7.5.1.5 Serial Register Write: Digital Bank
        6. 7.5.1.6 Individual Channel Programming
        7. 7.5.1.7 Serial Register Readout: JESD Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 SERDES Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Information
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1 General Registers
          1. 7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
          2. 7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
          3. 7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
          4. 7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
        2. 7.6.3.2 Master Page (80h)
          1. 7.6.3.2.1  Register 20h (address = 20h) [reset = 0h], Master Page (080h)
          2. 7.6.3.2.2  Register 21h (address = 21h) [reset = 0h], Master Page (080h)
          3. 7.6.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.2.4  Register 24h (address = 24h) [reset = 0h], Master Page (080h)
          5. 7.6.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.2.6  Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
          7. 7.6.3.2.7  Register 39h (address = 39h) [reset = 0h], Master Page (80h)
          8. 7.6.3.2.8  Register 53h (address = 53h) [reset = 0h], Master Page (80h)
          9. 7.6.3.2.9  Register 54h (address = 54h) [reset = 0h], Master Page (80h)
          10. 7.6.3.2.10 Register 55h (address = 55h) [reset = 0h], Master Page (80h)
          11. 7.6.3.2.11 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
          12. 7.6.3.2.12 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
        3. 7.6.3.3 ADC Page (0Fh)
          1. 7.6.3.3.1  Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
          2. 7.6.3.3.2  Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
          3. 7.6.3.3.3  Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.3.4  Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.3.5  Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.3.6  Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.3.7  Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
          8. 7.6.3.3.8  Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
          9. 7.6.3.3.9  Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
          10. 7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
        4. 7.6.3.4 Interleaving Engine Page (6100h)
          1. 7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        5. 7.6.3.5 Decimation Filter Page (6141h) Registers
          1. 7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
          2. 7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
          3. 7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
        6. 7.6.3.6 Main Digital Page (6800h) Registers
          1. 7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        7. 7.6.3.7 JESD Digital Page (6900h) Registers
          1. 7.6.3.7.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.7.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.7.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.7.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.7.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.7.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.7.7 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.7.8 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        8. 7.6.3.8 JESD Analog Page (6A00h) Register
          1. 7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.8.2 Register 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.8.3 Register 17h (address = 17h) [reset = 0h], JESD Analog Page (6A00h)
          4. 7.6.3.8.4 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6A00h)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
        1. 8.1.2.1 Register Initialization
        2. 8.1.2.2 115
      3. 8.1.3 SYSREF Signal
      4. 8.1.4 SNR and Clock Jitter
      5. 8.1.5 Idle Channel Histogram
      6. 8.1.6 ADC Test Pattern
        1. 8.1.6.1 ADC Section
        2. 8.1.6.2 Transport Layer Pattern
        3. 8.1.6.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Sequencing and Initialization
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.6.3.3.3 Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
Figure 7-53 Register 61h
76543210
0000HD3 NYQ2 CHCD00PULSE BIT CHD
W-0hW-0hW-0hW-0hR/W-0hW-0hW-0hR/W-0h
Table 7-36 Register 61h Field Descriptions
BitNameTypeResetDescription
7-40W0hMust write 0.
3HD3 NYQ2 CHCDR/W0hSet this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel C and D. When this bit is set, the PULSE BIT CHx register bits must be pulsed to obtain the improvement in corresponding channels.
2-10W0hMust write 0.
0PULSE BIT CHDR/W0hPulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel D.(1)
Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.
(1) Pulsing = set the bit to 1 and then reset to 0.