The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz.
In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain.
Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package.
The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates.
The device is specified over the industrial temperature range of –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS5560 | VQFN (48) | 7.00 mm × 7.00 mm |
ADS5562 |
Changes from A Revision (May 2012) to B Revision
Changes from * Revision (May 2008) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
9, 12, 14, 17, 19, 25 | AGND | I | Analog ground |
8, 18, 20, 22, 24, 26 |
AVDD | I | Analog power supply |
4 | CLKOUTM | O | Differential output clock, complement |
5 | CLKOUTP | O | Differential output clock, true |
10 | CLKP | I | Differential clock input |
11 | CLKM | ||
31 | D0_D1_M | O | Differential output data D0 and D1 multiplexed, complement. |
32 | D0_D1_P | O | Differential output data D0 and D1 multiplexed, true |
43 | D10_D11_M | O | Differential output data D10 and D11 multiplexed, complement |
44 | D10_D11_P | O | Differential output data D10 and D11 multiplexed, true |
45 | D12_D13_M | O | Differential output data D12 and D13 multiplexed, complement |
46 | D12_D13_P | O | Differential output data D12 and D13 multiplexed, true |
47 | D14_D15_M | O | Differential output data D14 and D15 multiplexed, complement |
48 | D14_D15_P | O | Differential output data D14 and D15 multiplexed, true |
33 | D2_D3_M | O | Differential output data D2 and D3 multiplexed, complement |
34 | D2_D3_P | O | Differential output data D2 and D3 multiplexed, true |
37 | D4_D5_M | O | Differential output data D4 and D5 multiplexed, complement |
38 | D4_D5_P | O | Differential output data D4 and D5 multiplexed, true |
39 | D6_D7_M | O | Differential output data D6 and D7 multiplexed, complement |
40 | D6_D7_P | O | Differential output data D6 and D7 multiplexed, true |
41 | D8_D9_M | O | Differential output data D8 and D9 multiplexed, complement |
42 | D8_D9_P | O | Differential output data D8 and D9 multiplexed, true |
6 | DFS | I | Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output mode type. See Table 7 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
1, 36 | DRGND | I | Digital and output buffer ground |
2, 35 | DRVDD | I | Digital and output buffer supply |
15 | INP | I | Differential analog input |
16 | INM | ||
23 | MODE | I | Mode select input. This pin selects the Internal or External reference mode. See Table 8 for detailed information. The pin has an internal 100-kΩ pulldown resistor to AGND. |
21 | NC | — | Do not connect |
7 | OE | I | Output buffer enable input, active high. The pin has an internal 100-kΩ pullup resistor to DRVDD. |
3 | OVR | O | Out-of-range indicator, CMOS level signal |
30 | RESET | I | Serial interface reset input. When using the serial interface, the user should apply a high-going pulse on this pin to reset the internal registers. When the serial interface is not used, the user should tie RESET permanently high. (SCLK, SDATA and SEN can be used as parallel pin controls). The pin has an internal 100-kΩ pulldown resistor to DRGND. |
29 | SCLK | I | This pin functions as serial interface clock input when RESET is low. It functions as LOW SPEED MODE control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
28 | SDATA | I | This pin functions as serial interface data input when RESET is low. It functions as STANDBY control pin when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
27 | SEN | I | This pin functions as serial interface enable input when RESET is low. It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed information. The pin has an internal 100-kΩ pullup resistor to DRVDD. |
13 | VCM | I/O | Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the internal reference. |
— | PAD | — | Connect the PAD to the ground plane. See the Exposed Thermal Pad section. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
9, 12, 14, 17, 19, 25 | AGND | I | Analog ground |
8, 18, 20, 22, 24, 26 |
AVDD | I | Analog power supply |
5 | CLKOUT | O | CMOS output clock |
10 | CLKP | I | Differential clock input |
11 | CLKM | ||
31 | D0 | O | CMOS output data D0 |
32 | D1 | O | CMOS output data D1 |
43 | D10 | O | CMOS output data D10 |
44 | D11 | O | CMOS output data D11 |
45 | D12 | O | CMOS output data D12 |
46 | D13 | O | CMOS output data D13 |
47 | D14 | O | CMOS output data D14 |
48 | D15 | O | CMOS output data D15 |
33 | D2 | O | CMOS output data D2 |
34 | D3 | O | CMOS output data D3 |
37 | D4 | O | CMOS output data D4 |
38 | D5 | O | CMOS output data D5 |
39 | D6 | O | CMOS output data D6 |
40 | D7 | O | CMOS output data D7 |
41 | D8 | O | CMOS output data D8 |
42 | D9 | O | CMOS output data D9 |
6 | DFS | I | Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output mode type. See Table 7 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
1, 36 | DRGND | I | Digital and output buffer ground |
2, 35 | DRVDD | I | Digital and output buffer supply |
15 | INP | I | Differential analog input |
16 | INM | ||
23 | MODE | I | Mode select input. This pin selects the Internal or External reference mode. See Table 8 for detailed information. The pin has an internal 100-kΩ pulldown resistor to AGND. |
21 | NC | — | Do not connect |
7 | OE | I | Output buffer enable input, active high. The pin has an internal 100-kΩ pullup resistor to DRVDD. |
3 | OVR | O | Out-of-range indicator, CMOS level signal |
30 | RESET | I | Serial interface reset input. When using the serial interface, the user should apply a high-going pulse on this pin to reset the internal registers. When the serial interface is not used, the user should tie RESET permanently high. (SCLK, SDATA and SEN can be used as parallel pin controls). The pin has an internal 100-kΩ pulldown resistor to DRGND. |
29 | SCLK | I | This pin functions as serial interface clock input when RESET is low. It functions as LOW SPEED MODE control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
28 | SDATA | I | This pin functions as serial interface data input when RESET is low. It functions as STANDBY control pin when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100-kΩ pulldown resistor to DRGND. |
27 | SEN | I | This pin functions as serial interface enable input when RESET is low. It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed information. The pin has an internal 100-kΩ pullup resistor to DRVDD. |
4 | UNUSED | — | Unused pin in CMOS mode |
13 | VCM | I/O | Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the internal references. |
— | PAD | — | Connect the PAD to the ground plane. See the Exposed Thermal Pad section. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage | AVDD | –0.3 | 3.9 | V | |
DRVDD | –0.3 | 3.9 | V | ||
Voltage between AGND and DRGND | –0.3 | 0.3 | V | ||
Voltage between AVDD and DRVDD | –0.3 | 3.3 | V | ||
Voltage applied to VCM pin (in external reference mode) | –0.3 | 1.8 | V | ||
Voltage applied to analog input pins | INP, INM | –0.3 | (3.6, AVDD + 0.3 ) | V | |
CLKP, CLKM(2), MODE | –0.3 | (3.6, AVDD + 0.3 ) | |||
RESET, SCLK, SDATA, SEN, OE, DFS | –0.3 | (3.6, DRVDD + 0.3 ) | V | ||
TA | Operating free-air temperature | –40 | 85 | °C | |
Tjmax | Operating junction temperature | 125 | °C | ||
Lead temperature 1,6 mm (1/16") from the case for 10 s | 220 | °C | |||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 500 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
SUPPLIES AND REFERENCES | |||||||
AVDD | Analog supply voltage | 3 | 3.3 | 3.6 | V | ||
DRVDD | Digital supply voltage | 3 | 3.3 | 3.6 | V | ||
ANALOG INPUTS | |||||||
Differential input voltage range (with default fine gain=1 dB) | 3.56 | VPP | |||||
Input common-mode voltage | 1.5 ±0.1 | V | |||||
Voltage applied on VCM in external reference mode | 1.5 ±0.05 | V | |||||
CLOCK INPUT | |||||||
Sample rate | ADS5562 | DEFAULT SPEED mode | > 25 | 80 | MSPS | ||
LOW SPEED mode(2) | 1 | 25 | MSPS | ||||
ADS5560 | DEFAULT SPEED mode | > 25 | 40 | MSPS | |||
LOW SPEED mode | 1 | 25 | MSPS | ||||
Clock amplitude, ac-coupled, differential (VCLKP – VCLKM)(1) | 0.4 | VPP | |||||
Clock duty cycle | 45% | 50% | 55% | ||||
DIGITAL OUTPUTS | |||||||
CL | Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes) | 5 | pF | ||||
RL | Differential external load resistance between the LVDS output pairs (LVDS mode) | 100 | Ω | ||||
Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | ADS5560 ADS5562 |
UNIT | |
---|---|---|---|
RGZ (VQFN) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 27.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 12.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 4.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 4.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Resolution | 16 | bits | |||||
ANALOG INPUT | |||||||
Differential input voltage range (1) | 3.56 | VPP | |||||
Differential input capacitance | 5 | pF | |||||
Analog input bandwidth | 300 | MHz | |||||
Analog input common-mode current (per input pin) | 6.6 | μA/MSPS | |||||
VCM | Common-mode output voltage | Internal reference mode | 1.5 | V | |||
VCM output current capability | Internal reference mode | ±4 | mA | ||||
DC ACCURACY | |||||||
No Missing Codes | 0-dB gain | Assured | |||||
DNL | Differential non-linearity | –0.95 | 0.5 | 3 | LSB | ||
INL | Integral non-linearity | –8.5 | ±3 | 8.5 | LSB | ||
Offset error | –25 | ±10 | 25 | mV | |||
Offset error temperature coefficient | 0.005 | mV/°C | |||||
Variation of offset error across AVDD supply | 1.5 | mV/V | |||||
There are two sources of gain error: I) internal reference inaccuracy and ii) channel gain error | |||||||
EGREF | Gain error due to internal reference inaccuracy alone | –2.5 | ±1 | 2.5 | % full scale | ||
ECHAN | Channel gain error alone | –2.5 | ± 1 | 2.5 | % full scale | ||
Channel gain error temperature coefficient | 0.01 | Δ%/°C | |||||
POWER SUPPLY | |||||||
IAVDD | Analog supply current | ADS5560 | 210 | 250 | mA | ||
ADS5562 | 160 | 190 | |||||
IDRVDD | Digital supply current | LVDS mode CL = 5 pF, IO = 3.5 mA, RL = 100 Ω |
ADS5560 | 52 | mA | ||
ADS5562 | 44 | ||||||
CMOS mode CL = 5 pF, FIN = 3 MHz |
ADS5560 | 60 | mA | ||||
ADS5562 | 37 | ||||||
Total power | LVDS mode | ADS5560 | 865 | 1100 | mW | ||
ADS5562 | 674 | 810 | |||||
Standby power | STANDBY mode with clock running | ADS5560 | 155 | mW | |||
ADS5562 | 135 | ||||||
Clock stop power | 125 | 150 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SNR Signal to noise ratio |
LVDS interface | FIN = 3 MHz | 84.3 | dBFS | ||
FIN = 10 MHz | 80 | 84 | ||||
FIN = 25 MHz | 82.5 | |||||
FIN = 30 MHz | 81.8 | |||||
CMOS interface | FIN = 3 MHz | 83.5 | dBFS | |||
FIN = 10 MHz | 78 | 83.1 | ||||
FIN = 25 MHz | 81.8 | |||||
FIN = 30 MHz | 81.6 | |||||
RMS output noise | Inputs tied to common-mode | 1.42 | LSB | |||
SINAD Signal to noise and distortion ratio |
LVDS interface | FIN = 3 MHz | 83.2 | dBFS | ||
FIN = 10 MHz | 76 | 83 | ||||
FIN = 25 MHz | 79 | |||||
FIN = 30 MHz | 77 | |||||
CMOS interface | FIN = 3 MHz | 82 | dBFS | |||
FIN = 10 MHz | 75 | 81.4 | ||||
FIN = 25 MHz | 79.3 | |||||
FIN = 30 MHz | 78 | |||||
ENOB Effective number of bits |
LVDS interface, FIN = 10 MHz | 12.4 | 13.5 | bits | ||
SFDR Spurious free dynamic range |
FIN = 3 MHz | 90 | dBc | |||
FIN = 10 MHz | 78 | 88 | ||||
FIN = 25 MHz | 83 | |||||
FIN = 30 MHz | 79 | |||||
HD2 Second harmonic |
FIN = 3 MHz | 94 | dBc | |||
FIN = 10 MHz | 78 | 92 | ||||
FIN = 25 MHz | 90 | |||||
FIN = 30 MHz | 88 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SNR Signal to noise ratio |
LVDS interface | FIN = 3 MHz | 84 | dBFS | ||
FIN = 10 MHz | 79 | 83.8 | ||||
FIN = 25 MHz | 83.2 | |||||
FIN = 30 MHz | 82.8 | |||||
CMOS interface | FIN = 3 MHz | 81.7 | dBFS | |||
FIN = 10 MHz | 77 | 81.4 | ||||
FIN = 25 MHz | 80.7 | |||||
FIN = 30 MHz | 80.4 | |||||
RMS output noise | Inputs tied to common-mode | 1.42 | LSB | |||
SINAD Signal to noise and distortion ratio |
LVDS interface | FIN = 3 MHz | 80.5 | dBFS | ||
FIN = 10 MHz | 75 | 80.5 | ||||
FIN = 25 MHz | 79.5 | |||||
FIN = 30 MHz | 79 | |||||
CMOS interface | FIN = 3 MHz | 80.5 | dBFS | |||
FIN = 10 MHz | 73.5 | 80.2 | ||||
FIN = 25 MHz | 79.3 | |||||
FIN = 30 MHz | 77.9 | |||||
ENOB Effective number of bits |
LVDS interface, FIN = 10 MHz | 12.2 | 13.1 | bits | ||
SFDR Spurious free dynamic range |
FIN = 3 MHz | 85 | dBc | |||
FIN = 10 MHz | 77 | 85 | ||||
FIN = 25 MHz | 83 | |||||
FIN = 30 MHz | 80 | |||||
HD2 Second harmonic |
FIN = 3 MHz | 90 | dBc | |||
FIN = 10 MHz | 77 | 89 | ||||
FIN = 25 MHz | 88 | |||||
FIN = 30 MHz | 88 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
HD3 Third harmonic |
FIN = 3 MHz | 85 | dBc | |||
FIN = 10 MHz | 77 | 85 | ||||
FIN = 25 MHz | 83 | |||||
FIN = 30 MHz | 80 | |||||
Worst harmonic other than HD2, HD3 |
FIN = 3 MHz | 104 | dBc | |||
FIN = 10 MHz | 102 | |||||
FIN = 25 MHz | 100 | |||||
FIN = 30 MHz | 100 | |||||
THD Total harmonic distortion |
FIN = 3 MHz | 84 | dBc | |||
FIN = 10 MHz | 75.5 | 83 | ||||
FIN = 25 MHz | 82 | |||||
FIN = 30 MHz | 80 | |||||
IMD Two-tone intermodulation distortion |
FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS | 92 | dBFS | |||
Voltage overload recovery time | Recovery to 1% for 6-dB overload | 1 | clock cycles |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
HD3 Third harmonic |
FIN = 3 MHz | 90 | dBc | |||
FIN = 10 MHz | 78 | 88 | ||||
FIN = 25 MHz | 83 | |||||
FIN = 30 MHz | 79 | |||||
Worst harmonic other than HD2, HD3 |
FIN = 3 MHz | 104 | dBc | |||
FIN = 10 MHz | 102 | |||||
FIN = 25 MHz | 101 | |||||
FIN = 30 MHz | 101 | |||||
THD Total harmonic distortion |
FIN = 3 MHz | 88 | dBc | |||
FIN = 10 MHz | 76.5 | 86 | ||||
FIN = 25 MHz | 81 | |||||
FIN = 30 MHz | 78 | |||||
IMD Two-tone intermodulation distortion |
FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS | 98 | dBFS | |||
Voltage overload recovery time | Recovery to 1% for 6-dB overload | 1 | clock cycles |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
DIGITAL INPUTS | |||||
High-level input voltage | 2.4 | V | |||
Low-level input voltage | 0.8 | V | |||
High-level input current | 33 | μA | |||
Low-level input current | –33 | μA | |||
Input capacitance | 4 | pF | |||
DIGITAL OUTPUTS – CMOS MODE | |||||
High-level output voltage | DRVDD | V | |||
Low-level output voltage | 0 | V | |||
Output capacitance | Capacitance inside the device from each output pin to ground | 4 | pF | ||
DIGITAL OUTPUTS – LVDS MODE | |||||
High-level output voltage, VODH | 350 | mV | |||
Low-level output voltage, VODL | –350 | mV | |||
Output common-mode voltage, VOCM | 1.2 | V | |||
Output capacitance | Capacitance inside the device from each output pin to ground | 4 | pF |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
ta | Aperture delay | 0.5 | 1.2 | 2 | ns | ||
tj | Aperture jitter | Sampling frequency = 80 MSPS | 90 | fs rms | |||
Sampling frequency = 40 MSPS | 135 | fs rms | |||||
Wake-up time | Time to data stable(8) after coming out of STANDBY mode | 60 | 200 | μs | |||
Time to valid data after stopping and restarting the input clock | 80 | μs | |||||
Latency | 16 | Clock cycles | |||||
DDR LVDS MODE(4) | |||||||
LVDS bit clock duty cycle | 47% | 50% | 53% | ||||
tsu | Data setup time(5) | Data valid(6) to zero-crossing of CLKOUTP | 2 | 3 | ns | ||
th | Data hold time(5) | Zero-crossing of CLKOUTP to data becoming invalid(6) | 2 | 3 | ns | ||
tPDI | Clock propagation delay | Input clock rising edge cross-over to output clock rising edge cross-over | 9.5 | 11 | 12.5 | ns | |
tr | Data rise time | Rise time measured from –100 mV to 100 mV | 0.15 | 0.22 | 0.3 | ns | |
tf | Data fall time | Fall time measured from 100 mV to –100 mV | 0.15 | 0.22 | 0.3 | ns | |
tr | Output clock rise time | Rise time measured from –100 mV to 100 mV | 0.15 | 0.22 | 0.3 | ns | |
tf | Output clock fall time | Fall time measured from 100 mV to –100 mV | 0.15 | 0.22 | 0.3 | ns | |
tOE | Output enable (OE) to data delay | Time to data valid after OE becomes active | 700 | ns | |||
PARALLEL CMOS MODE | |||||||
CMOS output clock duty cycle | 50% | ||||||
tsu | Data setup time | Data valid(7) to 50% of CLKOUT rising edge | 6.5 | 8 | ns | ||
th | Data hold time | 50% of CLKOUT rising edge to data becoming invalid (7) | 2 | 3 | ns | ||
tPDI | Clock propagation delay | Input clock rising edge cross-over to 50% of CLKOUT rising edge | 6.3 | 7.8 | 9.3 | ns | |
tr | Data rise time | Rise time measured from 20% to 80% of DRVDD | 1 | 1.5 | 2 | ns | |
tf | Data fall time | Fall time measured from 80% to 20% of DRVDD | 1 | 1.5 | 2 | ns | |
tr | Output clock rise time | Rise time measured from 20% to 80% of DRVDD | 0.7 | 1 | 1.2 | ns | |
tf | Output clock fall time | Fall time measured from 80% to 20% of DRVDD | 1.2 | 1.5 | 1.8 | ns | |
tOE | Output enable (OE) to data delay | Time to data valid after OE becomes active | 200 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency | > DC | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDATA setup time | 25 | ns | ||
tDH | SDATA hold time | 25 | ns |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
t1 | Power-on delay | Delay from power-up of AVDD and DRVDD to RESET pulse active | 5 | ms | ||
t2 | Reset pulse width | Pulse width of active RESET signal | 10 | ns | ||
1 | μs | |||||
t3 | Register write delay | Delay from RESET disable to SEN active | 25 | ns | ||
tPO | Power-up time | Delay from power-up of AVDD and DRVDD to output stable | 6.5 | ms |
NOTE:
A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. If the pulse is greater than 1 µs, the device could enter the parallel configuration mode briefly then return back to serial interface mode. For parallel interface operation, RESET must be tied permanently HIGH.