SBAS807B
January 2017 – December 2021
ADS58J64
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
AC Performance
6.7
Digital Characteristics
6.8
Timing Characteristics
6.9
Typical Characteristics: 14-Bit Burst Mode
6.10
Typical Characteristics: Mode 2
6.11
Typical Characteristics: Mode 0
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Inputs
7.3.2
Recommended Input Circuit
7.3.3
Clock Input
7.4
Device Functional Modes
7.4.1
Digital Features
7.4.1.1
Numerically Controlled Oscillators (NCOs) and Mixers
7.4.1.2
Decimation Filter
7.4.1.2.1
Stage-1 Filter
7.4.1.2.2
Stage-2 Filter
7.4.1.3
Mode 0: Decimate-by-4 With IQ Outputs and fS / 4 Mixer
7.4.1.4
Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO
7.4.1.5
Mode 2: Decimate-by-4 With Real Output
7.4.1.6
Mode 3: Decimate-by-2 Real Output With Frequency Shift
7.4.1.7
Mode 4: Decimate-by-4 With Real Output
7.4.1.8
Mode 6: Decimate-by-4 With IQ Outputs for up to 110 MHz of IQ Bandwidth
7.4.1.9
Mode 7: Decimate-by-4 With Real Output and Zero Stuffing
7.4.1.10
Mode 8: Burst Mode
7.4.1.11
Trigger Input
7.4.1.12
Manual Trigger Mode
7.4.1.13
Auto Trigger Mode
7.4.1.14
Overrange Indication
7.5
Programming
7.5.1
JESD204B Interface
7.5.2
JESD204B Initial Lane Alignment (ILA)
7.5.3
JESD204B Frame Assembly
7.5.4
JESD Output Switch
7.5.4.1
SerDes Transmitter Interface
7.5.4.2
SYNCb Interface
7.5.4.3
Eye Diagram
7.5.5
Device Configuration
7.5.5.1
Details of the Serial Interface
7.5.5.1.1
Register Initialization
7.5.5.2
Serial Register Write
7.5.5.3
Serial Read
7.6
Register Maps
7.6.1
Register Map
7.6.1.1
Register Description
7.6.1.1.1
GLOBAL Page Register Description
7.6.1.1.1.1
Register 00h (address = 00h) [reset = 0h], GLOBAL Page
7.6.1.1.1.2
Register 04h (address = 04h) [reset = 0h], GLOBAL Page
7.6.1.1.1.3
Register 11h (address = 11h) [reset = 0h], GLOBAL Page
7.6.1.1.1.4
Register 12h (address = 12h) [reset = 0h], GLOBAL Page
7.6.1.1.1.5
Register 13h (address = 13h) [reset = 0h], GLOBAL Page
7.6.1.1.2
DIGTOP Page Register Description
7.6.1.1.2.1
Register 64h (address = 64h) [reset = 0h], DIGTOP Page
7.6.1.1.2.2
Register 8Dh (address = 8Dh) [reset = 0h], DIGTOP Page
7.6.1.1.2.3
Register 8Eh (address = 8Eh) [reset = 0h], DIGTOP Page
7.6.1.1.2.4
Register 8Fh (address = 8Fh) [reset = 0h], DIGTOP Page
7.6.1.1.2.5
Register 90h (address = 90h) [reset = 0h], DIGTOP Page
7.6.1.1.2.6
Register 91h (address = 91h) [reset = 0h], DIGTOP Page
7.6.1.1.2.7
Register ABh (address = ABh) [reset = 0h], DIGTOP Page
7.6.1.1.2.8
Register ACh (address = ACh) [reset = 0h], DIGTOP Page
7.6.1.1.2.9
Register ADh (address = ADh) [reset = 0h], DIGTOP Page
7.6.1.1.2.10
Register AEh (address = AEh) [reset = 0h], DIGTOP Page
7.6.1.1.2.11
Register B7h (address = B7h) [reset = 0h], DIGTOP Page
7.6.1.1.3
ANALOG Page Register Description
7.6.1.1.3.1
Register 6Ah (address = 6Ah) [reset = 0h], ANALOG Page
7.6.1.1.3.2
Register 6Fh (address = 6Fh) [reset = 0h], ANALOG Page
7.6.1.1.3.3
Register 71h (address = 71h) [reset = 0h], ANALOG Page
7.6.1.1.3.4
Register 72h (address = 72h) [reset = 0h], ANALOG Page
7.6.1.1.3.5
Register 93h (address = 93h) [reset = 0h], ANALOG Page
7.6.1.1.3.6
Register 94h (address = 94h) [reset = 0h], ANALOG Page
7.6.1.1.3.7
Register 9Bh (address = 9Bh) [reset = 0h], ANALOG Page
7.6.1.1.3.8
Register 9Dh (address = 9Dh) [reset = 0h], ANALOG Page
7.6.1.1.3.9
Register 9Eh (address = 9Eh) [reset = 0h], ANALOG Page
7.6.1.1.3.10
Register 9Fh (address = 9Fh) [reset = 0h], ANALOG Page
7.6.1.1.3.11
Register AFh (address = AFh) [reset = 0h], ANALOG Page
7.6.1.1.4
SERDES_XX Page Register Description
7.6.1.1.4.1
Register 20h (address = 20h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.2
Register 21h (address = 21h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.3
Register 22h (address = 22h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.4
Register 23h (address = 23h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.5
Register 25h (address = 25h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.6
Register 26h (address = 26h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.7
Register 28h (address = 28h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.8
Register 2Dh (address = 2Dh) [reset = 0h], SERDES_XX Page
7.6.1.1.4.9
Register 36h (address = 36h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.10
Register 37h (address = 37h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.11
Register 39h (address = 39h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.12
Register 3Ah (address = 3Ah) [reset = 0h], SERDES_XX Page
7.6.1.1.4.13
Register 3Bh (address = 3Bh) [reset = 0h], SERDES_XX Page
7.6.1.1.4.14
Register 3Ch (address = 3Ch) [reset = 0h], SERDES_XX Page
7.6.1.1.4.15
Register 3Dh (address = 3Dh) [reset = 0h], SERDES_XX Page
7.6.1.1.4.16
Register 3Eh (address = 3Eh) [reset = 0h], SERDES_XX Page
7.6.1.1.4.17
Register 3Fh (address = 3Fh) [reset = 0h], SERDES_XX Page
7.6.1.1.4.18
Register 40h (address = 40h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.19
Register 41h (address = 41h) [reset = 0h], SERDES_XX Page
7.6.1.1.4.20
Register 42h (address = 42h) [reset = 0h], SERDES_XX Page
7.6.1.1.5
CHX Page Register Description
7.6.1.1.5.1
Register 26h (address = 26h) [reset = 0h], CHX Page
7.6.1.1.5.2
Register 27h (address = 27h) [reset = 0h], CHX Page
7.6.1.1.5.3
Register 2Dh (address = 2Dh) [reset = 0h], CHX Page
7.6.1.1.5.4
Register 78h (address = 78h) [reset = 0h], CHX Page
7.6.1.1.5.5
Register 7Ah (address = 7Ah) [reset = 0h], CHX Page
7.6.1.1.5.6
Register 7Bh (address = 7Bh) [reset = 0h], CHX Page
7.6.1.1.5.7
Register 7Eh (address = 7Eh) [reset = 3h], CHX Page
7.6.1.1.6
ADCXX Page Register Description
7.6.1.1.6.1
Register 07h (address = 07h) [reset = FFh], ADCXX Page
7.6.1.1.6.2
Register 08h (address = 08h) [reset = 0h], ADCXX Page
7.6.1.1.6.3
Register D5h (address = D5h) [reset = 0h], ADCXX Page
8
Application and Implementation
8.1
Application Information
8.1.1
Start-Up Sequence
8.1.2
Hardware Reset
8.1.3
Frequency Planning
8.1.4
SNR and Clock Jitter
8.1.5
ADC Test Pattern
8.1.5.1
ADC Section
8.1.5.2
Transport Layer Pattern
8.1.5.3
Link Layer Pattern
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RMP|72
MPQF396A
RRH|72
MPQF526
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbas807b_oa
sbas807b_pm
7.6.1.1.1
GLOBAL Page Register Description