SBAS819 December 2017 ADS7047
PRODUCTION DATA.
MIN | MAX | UNIT | |
---|---|---|---|
AVDD to GND | –0.3 | 3.9 | V |
DVDD to GND | –0.3 | 3.9 | V |
AINP to GND | –0.3 | AVDD + 0.3 | V |
AINM to GND | –0.3 | AVDD + 0.3 | V |
Input current to any pin except supply pins | –10 | 10 | mA |
Digital input voltage to GND | –0.3 | DVDD + 0.3 | V |
Storage temperature, Tstg | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog supply voltage range | 2.35 | 3.3 | 3.6 | V |
DVDD | Digital supply voltage range | 1.65 | 1.8 | 3.6 | V |
TA | Operating free-air temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ADS7047 | UNIT | |
---|---|---|---|
RUG (X2QFN) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 177.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 76.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 76.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input voltage span(1) | –AVDD | AVDD | V | |||
Absolute input voltage range | AINP to GND | –0.1 | AVDD + 0.1 | V | ||
AINM to GND | –0.1 | AVDD + 0.1 | ||||
Common-mode voltage | (AINP + AINM) / 2 | (AVDD / 2) – 0.1 | (AVDD / 2) + 0.1 | V | ||
CS | Sampling capacitance | 16 | pF | |||
SYSTEM PERFORMANCE | ||||||
Resolution | 12 | Bits | ||||
NMC | No missing codes | 12 | Bits | |||
INL(8) | Integral nonlinearity | –0.75 | ±0.2 | 0.75 | LSB(2) | |
DNL | Differential nonlinearity | –0.5 | ±0.15 | 0.5 | LSB | |
EO(8) | Offset error | After calibration(7) | –3 | ±1 | 3 | LSB |
dVOS/dT | Offset error drift with temperature | 1.75 | ppm/°C | |||
EG(8) | Gain error | –0.1 | ±0.01 | 0.1 | %FS | |
Gain error drift with temperature | 0.5 | ppm/°C | ||||
SAMPLING DYNAMICS | ||||||
tCONV | Conversion time | 15 × tSCLK | ns | |||
tACQ | Acquisition time | 80 | ns | |||
fSAMPLE | Maximum throughput rate | 60-MHz SCLK, AVDD = 2.35 V to 3.6 V | 3 | MHz | ||
Aperture delay | 3 | ns | ||||
Aperture jitter, RMS | 12 | ps | ||||
DYNAMIC CHARACTERISTICS | ||||||
SNR | Signal-to-noise ratio(4) | AVDD = 3.3 V, fIN = 2 kHz | 70 | 72.9 | dB | |
AVDD = 2.5 V, fIN = 2 kHz | 72.5 | |||||
THD | Total harmonic distortion(4)(3) | fIN = 2 kHz | –90 | dB | ||
fIN = 500 kHz | –88 | |||||
fIN = 1000 kHz | –88 | |||||
SINAD | Signal-to-noise and distortion(4) | fIN = 2 kHz | 69.5 | 72.8 | dB | |
fIN = 500 kHz | 72.7 | |||||
fIN = 1000 kHz | 72.7 | |||||
SFDR | Spurious-free dynamic range(4) | fIN = 2 kHz | 95 | dB | ||
fIN = 500 kHz | 89.8 | |||||
fIN = 1000 kHz | 89.7 | |||||
BW(fp) | Full-power bandwidth | At –3 dB | 200 | MHz | ||
DIGITAL INPUT/OUTPUT (CMOS Logic Family) | ||||||
VIH | High-level input voltage(5) | 0.65 DVDD | DVDD + 0.3 | V | ||
VIL | Low-level input voltage(5) | –0.3 | 0.35 DVDD | V | ||
VOH | High-level output voltage(5) | At Isource = 500 µA | 0.8 DVDD | DVDD | V | |
At Isource = 2 mA | DVDD – 0.45 | DVDD | ||||
VOL | Low-level output voltage(5) | At Isink = 500 µA | 0 | 0.2 DVDD | V | |
At Isink = 2 mA | 0 | 0.45 | ||||
POWER-SUPPLY REQUIREMENTS | ||||||
AVDD | Analog supply voltage | 2.35 | 3 | 3.6 | V | |
DVDD | Digital I/O supply voltage | 1.65 | 3 | 3.6 | V | |
IAVDD | Analog supply current | AVDD = 3.3 V, fSAMPLE = 3 MSPS | 1220 | 1400 | µA | |
AVDD = 3.3 V, fSAMPLE = 100 kSPS | 40 | 47 | ||||
AVDD = 3.3 V, fSAMPLE = 10 kSPS | 5 | |||||
AVDD = 2.5 V, fSAMPLE = 3 MSPS | 890 | |||||
Static current with CS and SCLK high | 0.02 | |||||
IDVDD | Digital supply current | DVDD = 1.8 V, CSDO = 20 pF, output code = AAAh(6) |
650 | µA | ||
DVDD = 1.8 V, static current with CS and SCLK high | 0.01 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tCLK | Time period of SCLK | 16.66 | ns | ||
tsu_CSCK | Setup time: CS falling edge to SCLK falling edge | 7 | ns | ||
tht_CKCS | Hold time: SCLK rising edge to CS rising edge | 8 | ns | ||
tph_CK | SCLK high time | 0.45 | 0.55 | tSCLK | |
tpl_CK | SCLK low time | 0.45 | 0.55 | tSCLK | |
tph_CS | CS high time | 15 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCYCLE(1) | Cycle time | 333 | ns | |||
tCONV | Conversion time | 15 × tSCLK | ns | |||
tden_CSDO | Delay time: CS falling edge to data enable | 6.5 | ns | |||
td_CKDO | Delay time: SCLK rising edge to (next) data valid on SDO | 10 | ns | |||
tht_CKDO | SCLK rising edge to current data invalid | 2.5 | ns | |||
tdz_CSDO | Delay time: CS rising edge to SDO going to tri-state | 5.5 | ns |
SNR = 73.2 dB, THD = –87.2 dB, ENOB = 11.8 bits |
SNR = 71.3dB, THD = –89.7 dB, fIN = 1000 kHz |
VIN = 0 (differential) |
SNR = 72.8 dB, THD = –82.1 dB, fIN = 500 kHz |
CS = DVDD |