SBAS859 December   2017 ADS7054

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Product Family
      2. 8.3.2 Analog Input
      3. 8.3.3 Reference
      4. 8.3.4 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 ACQ State
      2. 8.4.2 CNV State
      3. 8.4.3 OFFCAL State
        1. 8.4.3.1 Offset Calibration on Power-Up
        2. 8.4.3.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 2-Channel, Simultaneous Sampling Data Acquisition Using the ADS7054
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Low Distortion Charge Kickback Filter Design
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Improving Precision of Single-Ended Signal Source Measurements Using the ADS7054
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Optimizing Power Consumed by the Device
      1. 10.2.1 Estimating Digital Power Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The two primary supporting circuits required to maximize the performance of a high-precision, successive approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides typical application circuits designed for the device.

9.2 Typical Applications

9.2.1 2-Channel, Simultaneous Sampling Data Acquisition Using the ADS7054

ADS7054 apps1_diff_sbas769.gif Figure 40. 2-Channel, Simultaneous-Sampling Data Acquisition (DAQ) Circuit Using the ADS7054

9.2.1.1 Design Requirements

The goal of the circuit shown in Figure 40 is to design a two-channel, simultaneous-sampling data acquisition (DAQ) circuit based on the ADS7054 with an SNR greater than 79 dB and a THD less than –85 dB for input frequencies from 2 kHz to 50 kHz at a throughput of 1 MSPS. This simultaneous-sampling scheme is typically used in motor sine and cosine (sin-cos) encoders, resolvers, fish finders, sonar, and I-Q demodulation.

9.2.1.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.1.2.1 Low Distortion Charge Kickback Filter Design

Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched capacitor load can create stability issues.

ADS7054 diff_filter_sbas769.gif Figure 41. Input Sample-and-Hold Circuit for a Typical SAR ADC

For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.

9.2.1.2.2 Input Amplifier Selection

The input amplifier bandwidth is typically much higher than the cutoff frequency of the charge kickback filter. Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters. To learn more about the SAR ADC input driver design, see the TI Precision Labs training video series.

The THS4551 is selected for its high bandwidth (135 MHz), low total harmonic distortion of –90 dBc at 100 kHz, and ultra-low noise of (3.2 nV/√Hz). The THS4551 is powered up from the power supply (VDD = 5 V and VSS = GND).

9.2.1.2.3 Reference Circuit

The ADS70xx uses the analog supply voltage (AVDD) as the reference voltage for the analog-to-digital conversion. During the conversion process, the internal capacitors are switched to the level of the AVDD pin as per the successive approximation algorithm. A voltage reference must be selected with low temperature drift, high output current drive, and low output impedance. For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.

TI recommends a 3.3-μF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the AVDD pin.

9.2.1.3 Application Curves

Figure 42 and Figure 43 provide the measurement results for the circuit described in Figure 40.

ADS7054 D103_SBAS859.gif
Device 1 SNR = 80.3 dB, THD = –93 dB, SINAD = 79.6 dB
Device 2 SNR = 79.8 dB, THD = –92 dB, SINAD = 79.3 dB
Figure 42. Test Results for the ADS7054 and THS4551 for a 2-kHz input
ADS7054 D100_SBAS859.gif
Device 1 SNR = 79.2 dB, THD = –94 dB, SINAD = 78.9 dB
Device 2 SNR = 78.9 dB, THD = –92 dB, SINAD = 78.6 dB
Figure 43. Test Results for the ADS7054 and THS4551 for a 50-kHz input

9.2.2 Improving Precision of Single-Ended Signal Source Measurements Using the ADS7054

ADS7054 apps2_diff_sbas769.gif Figure 44. Interfacing Single-Ended Signals with the ADS7054 Using a Single-Ended to Differential
Front-End

9.2.2.1 Design Requirements

Some applications have sensor or signal inputs that are single ended. In order to increase the dynamic range, linearity, and precision of the system, such single-ended signals are often required to be interfaced with a differential input ADC. The goal of the design shown in Figure 44 is to interface a single-ended input source with the ADS7054 using a single-ended to differential front-end amplifier to achieve an SNR greater than 79 dB and a THD less than –85 dB for input frequencies up to 10 kHz at a throughput of 1 MSPS.

9.2.2.2 Detailed Design Procedure

To achieve a SNR greater than 79 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 44, the THS4551 is selected for its high bandwidth (135 MHz), low total harmonic distortion of –90 dBc at 100 kHz, and ultra-low noise of (3.2 nV/√Hz). The THS4551 is powered up from the power supply (VDD = 5 V and VSS = GND).

The THS4551 can be used in a single-ended to differential configuration as shown in Figure 44 without any performance degradation. This configuration enables single-ended input signals to be interfaced with differential input SAR ADCs (such as the ADS7054) to achieve higher system-level precision.

For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.

9.2.2.3 Application Curve

Figure 45 shows the FFT plot for the ADS7054 with a 2-kHz, single-ended input signal used for the circuit in Figure 44.

ADS7054 D102_SBAS859.gif
SNR = 79.8 dB, THD = –92 dB, SINAD = 79.1 dB
Figure 45. Test Results for the ADS7054 With a 2-kHz, Single-Ended Input