SBAS769 March   2017 ADS7056

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Reference
      3. 8.3.3 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 ACQ State
      2. 8.4.2 CNV State
      3. 8.4.3 OFFCAL State
        1. 8.4.3.1 Offset Calibration on Power-Up
        2. 8.4.3.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply Data Acquisition With the ADS7056
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Low Distortion Charge Kickback Filter Design
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High Bandwidth (1 MHz) Data Acquisition With the ADS7056
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Optimizing Power Consumed by the Device
      1. 10.2.1 Estimating Digital Power Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides typical application circuits designed for the device.

9.2 Typical Applications

9.2.1 Single-Supply Data Acquisition With the ADS7056

ADS7056 apps1_sbas769.gif Figure 43. DAQ Circuit: Single-Supply DAQ

9.2.1.1 Design Requirements

The goal of the circuit shown in Figure 43 is to design a single-supply data acquisition (DAQ) circuit based on the ADS7056 with SNR greater than 74 dB and THD less than –85 dB for input frequencies of 2 kHz to 100 kHz at a throughput of 2.5 MSPS for applications such as sonar receivers and ultrasonic flow meters.

9.2.1.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.1.2.1 Low Distortion Charge Kickback Filter Design

Figure 44 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched capacitor load can create stability issues.

ADS7056 ads7056-input-sample-hold-circuit-sbas769.gif Figure 44. Input Sample-and-Hold Circuit for a Typical SAR ADC

For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.

9.2.1.2.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:

  • Small-signal bandwidth: select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the Low Distortion Charge Kickback Filter Design section for details.) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. Select the amplifier with the unity-gain bandwidth (UGB) as described in Equation 2 to maintain the overall stability of the input driver circuit.
    • Equation 2. ADS7056 ads7056-unity-gain-bw-equation-sbas769.gif

    where

    • UGB = unity-gain bandwidth
  • Noise: noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. Generally, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. As Equation 3 explains, noise from the input driver circuit is band limited by designing a low cutoff frequency RC filter.
    • Equation 3. ADS7056 q_noise_bas608.gif

    where

    • V1/f_AMP_PP is the peak-to-peak flicker noise in µVRMS
    • en_RMS is the amplifier broadband noise
    • f–3dB is the –3-dB bandwidth of the RC filter and
    • NG is the noise gain of the front-end circuit, which is equal to 1 in the buffer configuration
  • Distortion: both the ADC and the input driver introduce distortion in a data acquisition block. To ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC.

For the application circuit of Figure 43, the OPA836 is selected for its high bandwidth (205 MHz), low noise (4.6 nV/√Hz), high output drive capacity (45 mA), and fast settling response (22 ns for 0.1% settling).

9.2.1.2.3 Reference Circuit

The analog supply voltage of the device is also used as a voltage reference for conversion. Decouple the AVDD pin with a 3.3-µF, low-ESR ceramic capacitor.

9.2.1.3 Application Curves

Figure 45 and Figure 46 provide the measurement results for the circuit described in Figure 43.

ADS7056 D036_SBAS769_old.gif
SNR = 75.8 dB, THD = –90.1 dB, SINAD = 75 dB
Figure 45. Test Results for the ADS7056 and OPA836 for a 2-kHz Input
ADS7056 D037_SBAS769_old.gif
SNR = 75 dB, THD = –88.7 dB, SINAD = 74.3 dB
Figure 46. Test Results for the ADS7056 and OPA836 for a 100-kHz Input

9.2.2 High Bandwidth (1 MHz) Data Acquisition With the ADS7056

ADS7056 apps2_sbas769.gif Figure 47. High Bandwidth DAQ Circuit

9.2.2.1 Design Requirements

Applications such as ultrasonic flow meters, global positioning systems (GPS), handheld radios, and motor controls need analog-to-digital converters that are interfaced to high-frequency sensors (200 kHz to 1 MHz). The goal of the circuit described in Figure 47 is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7056 with SNR greater than 73 dB and THD less than –85 dB for input frequencies of 200 kHz to 1 MHz at a throughput of 2.5 MSPS.

9.2.2.2 Detailed Design Procedure

To achieve a SINAD greater than 73 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 47, the THS4031 is selected for its high bandwidth (275 MHz), low total harmonic distortion of –90 dB at 1 MHz, and ultra-low noise of 1.6 nV/√Hz. The THS4031 is powered up from dual power supply (VDD = 6 V and VSS = –6 V).

For chip-select signals, high-frequency system SNR performance is highly dependent on jitter. Thus, selecting a clock source with very low jitter (< 20-ps RMS) is recommended.

9.2.2.3 Application Curves

Figure 48 shows the FFT plot for the ADS7056 with a 500-kHz input frequency used for the circuit in Figure 47. Figure 49 shows the FFT plot for the ADS7056 with a 1000-kHz input frequency used for the circuit in Figure 47.

ADS7056 D035_SBAS769_old.gif
SNR = 74.2 dB, THD = –90.4 dB, SINAD = 73.5 dB
Figure 48. Test Results for the ADS7056 and THS4031 for a 500-kHz Input
ADS7056 D038_SBAS769_old.gif
SNR = 73.5 dB, THD = –87.8 dB, SINAD = 73 dB
Figure 49. Test Results for the ADS7056 and THS4031 for a 1000-kHz Input

9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements

ADS7056 ads7056-interfacing-device-with-sensors-sbas769.gif Figure 50. Interfacing the Device Directly With Sensors

In applications such as environmental sensors, gas detectors, and smoke or fire detectors where the input is very slow moving and the sensor can be connected directly to the device operating at a lower throughput rate, a DAQ circuit can be designed without the input driver for the ADC. This type of a use case is of particular interest for applications in which the primary goal is to achieve the absolute lowest power, size, and cost. Typical applications that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and chemical).

9.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters.

Table 4. Design Parameters

DESIGN PARAMETER GOAL VALUE
Throughput 10 kSPS
SNR at 100 Hz 74 dB
THD at 100 Hz –85 dB
SINAD at 100 Hz 73 dB
ENOB 12 bits
Power 20 µW

9.2.3.2 Detailed Design Procedure

The ADS7056 can be directly interfaced with sensors at lower throughput without the need of an amplifier buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the desired accuracy because of the higher output impedance of the sensor. Figure 50 shows the simplified circuit for a sensor as a voltage source with output impedance (Rsource).

The acquisition time of a SAR ADC (such as the ADS7056 ) can be increased by reducing throughput in the following ways:

  1. Reducing the SCLK frequency to reduce the throughput, or
  2. Keeping the SCLK fixed at the highest permissible value (that is, 60 MHz for the device) and increasing the CS high time.

Table 5 lists the acquisition time for the above two cases for a throughput of 10 kSPS. Clearly, case 2 provides more acquisition time for the input signal to settle.

Table 5. Acquisition Time with Different SCLK Frequencies

CASE SCLK tcycle CONVERSION TIME
(= 18 × tSCLK)		 ACQUISITION TIME
(= tcycle – tconv)
1 0.24 MHz 100 µs 75 µs 25 µs
2 60 MHz 100 µs 0.3 µs 99.7 µs

9.2.3.3 Application Curve

When the output impedance of the sensor increases, the time required for the input signal to settle increases and the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time for the input signal to settle. Figure 51 provides the results for ENOB achieved from the ADS7056 for case 2 at different throughputs with different input impedances at the device input.

ADS7056 D039_SBAS769_old.gif Figure 51. Effective Number of Bits (ENOB) Achieved From the ADS7056 at Different Throughputs

Table 6 shows the results and performance summary for this 14-bit, 10-kSPS DAQ circuit application.

Table 6. Results and Performance Summary for a 14-Bit, 10-kSPS DAQ Circuit for DC Sensor Measurements

DESIGN PARAMETER GOAL VALUE ACHIEVED RESULT
Throughput 10 kSPS 10 kSPS
SNR at 100 Hz 74 dB 75 dB
THD at 100 Hz –85 dB –89 dB
SINAD at 100 Hz 73 dB 74.3 dB
ENOB 12 12.05
Power 20 µW 17 µW