The ADS7057 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices).
The ADS7057 is a 14-bit, 2.5-MSPS SAR ADC that supports fully-differential inputs in the range of ±AVDD, for AVDD in the range of 2.35 V to 3.6 V.
The internal offset calibration feature maintains excellent offset specifications over the entire AVDD and temperature operating range.
The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input signal is sampled with the CS falling edge and SCLK is used for both conversion and serial data output. The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host controllers. The ADS7057 complies with the JESD8-7A standard for a normal DVDD range (1.65 V to 1.95 V).
The ADS7057 is available in an 8-pin, small, X2QFN package and is specified over the extended industrial temperature range (–40°C to +125°C). The small form-factor and extremely-low power consumption make this device suitable for space-constrained and battery-powered applications that require high-speed, high-resolution data acquisition.
PART NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS7057 | X2QFN (8) | 1.50 mm × 1.50 mm |
DATE | REVISION | NOTES |
---|---|---|
December 2017 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CS | Digital input | Chip-select signal, active low |
2 | SDO | Digital output | Serial data out |
3 | SCLK | Digital input | Serial clock |
4 | DVDD | Supply | Digital I/O supply voltage |
5 | GND | Supply | Ground for power supply, all analog and digital signals are referred to this pin |
6 | AVDD | Supply | Analog power-supply input, also provides the reference voltage to the ADC |
7 | AINP | Analog input | Analog signal input, positive |
8 | AINM | Analog input | Analog signal input, negative |
MIN | MAX | UNIT | |
---|---|---|---|
AVDD to GND | –0.3 | 3.9 | V |
DVDD to GND | –0.3 | 3.9 | V |
AINP to GND | –0.3 | AVDD + 0.3 | V |
AINM to GND | –0.3 | AVDD + 0.3 | V |
Input current to any pin except supply pins | –10 | 10 | mA |
Digital input voltage to GND | –0.3 | DVDD + 0.3 | V |
Storage temperature, Tstg | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog supply voltage range | 2.35 | 3.3 | 3.6 | V |
DVDD | Digital supply voltage range | 1.65 | 1.8 | 3.6 | V |
TA | Operating free-air temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ADS7057 | UNIT | |
---|---|---|---|
RUG (X2QFN) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 177.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 76.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 76.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input voltage span(1) | –AVDD | AVDD | V | |||
Absolute input voltage range | AINP to GND | –0.1 | AVDD + 0.1 | V | ||
AINM to GND | –0.1 | AVDD + 0.1 | ||||
Common-mode voltage | (AINP + AINM) / 2 | (AVDD / 2) – 0.1 | (AVDD / 2) + 0.1 | V | ||
CS | Sampling capacitance | 16 | pF | |||
SYSTEM PERFORMANCE | ||||||
Resolution | 14 | Bits | ||||
NMC | No missing codes | 14 | Bits | |||
INL(8) | Integral nonlinearity | –3 | ±0.9 | 3 | LSB(2) | |
DNL | Differential nonlinearity | –0.99 | ±0.3 | 1 | LSB | |
EO(8) | Offset error | After calibration(7) | –6 | ±1 | 6 | LSB |
dVOS/dT | Offset error drift with temperature | 1.75 | ppm/°C | |||
EG(8) | Gain error | –0.1 | ±0.01 | 0.1 | %FS | |
Gain error drift with temperature | 0.5 | ppm/°C | ||||
SAMPLING DYNAMICS | ||||||
tCONV | Conversion time | 18 × tSCLK | ns | |||
tACQ | Acquisition time | 95 | ns | |||
fSAMPLE | Maximum throughput rate | 60-MHz SCLK, AVDD = 2.35 V to 3.6 V | 2.5 | MHz | ||
Aperture delay | 3 | ns | ||||
Aperture jitter, RMS | 12 | ps | ||||
DYNAMIC CHARACTERISTICS | ||||||
SNR | Signal-to-noise ratio(4) | AVDD = 3.3 V, fIN = 2 kHz | 76 | 79.6 | dB | |
AVDD = 2.5 V, fIN = 2 kHz | 78.5 | |||||
THD | Total harmonic distortion(4)(3) | fIN = 2 kHz | –92 | dB | ||
fIN = 500 kHz | –90.4 | |||||
fIN = 1000 kHz | –90.3 | |||||
SINAD | Signal-to-noise and distortion(4) | fIN = 2 kHz | 76 | 79.3 | dB | |
fIN = 500 kHz | 78.1 | |||||
fIN = 1000 kHz | 77.1 | |||||
SFDR | Spurious-free dynamic range(4) | fIN = 2 kHz | 95 | dB | ||
fIN = 500 kHz | 93.4 | |||||
fIN = 1000 kHz | 92.4 | |||||
BW(fp) | Full-power bandwidth | At –3 dB | 200 | MHz | ||
DIGITAL INPUT/OUTPUT (CMOS Logic Family) | ||||||
VIH | High-level input voltage(5) | 0.65 DVDD | DVDD + 0.3 | V | ||
VIL | Low-level input voltage(5) | –0.3 | 0.35 DVDD | V | ||
VOH | High-level output voltage(5) | At Isource = 500 µA | 0.8 DVDD | DVDD | V | |
At Isource = 2 mA | DVDD – 0.45 | DVDD | ||||
VOL | Low-level output voltage(5) | At Isink = 500 µA | 0 | 0.2 DVDD | V | |
At Isink = 2 mA | 0 | 0.45 | ||||
POWER-SUPPLY REQUIREMENTS | ||||||
AVDD | Analog supply voltage | 2.35 | 3 | 3.6 | V | |
DVDD | Digital I/O supply voltage | 1.65 | 3 | 3.6 | V | |
IAVDD | Analog supply current | AVDD = 3.3 V, fSAMPLE = 2.5 MSPS | 1100 | 1400 | µA | |
AVDD = 3.3 V, fSAMPLE = 100 kSPS | 47 | 56 | ||||
AVDD = 3.3 V, fSAMPLE = 10 kSPS | 5 | |||||
AVDD = 2.5 V, fSAMPLE = 2.5 MSPS | 820 | |||||
Static current with CS and SCLK high | 0.02 | |||||
IDVDD | Digital supply current | DVDD = 1.8 V, CSDO = 20 pF, output code = 2AAAh(6) |
630 | µA | ||
DVDD = 1.8 V, static current with CS and SCLK high | 0.01 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tCLK | Time period of SCLK | 16.66 | ns | ||
tsu_CSCK | Setup time: CS falling edge to SCLK falling edge | 7 | ns | ||
tht_CKCS | Hold time: SCLK rising edge to CS rising edge | 8 | ns | ||
tph_CK | SCLK high time | 0.45 | 0.55 | tSCLK | |
tpl_CK | SCLK low time | 0.45 | 0.55 | tSCLK | |
tph_CS | CS high time | 15 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCYCLE(1) | Cycle time | 400 | ns | |||
tCONV | Conversion time | 18 × tSCLK | ns | |||
tden_CSDO | Delay time: CS falling edge to data enable | 6.5 | ns | |||
td_CKDO | Delay time: SCLK rising edge to (next) data valid on SDO | 10 | ns | |||
tht_CKDO | SCLK rising edge to current data invalid | 2.5 | ns | |||
tdz_CSDO | Delay time: CS rising edge to SDO going to tri-state | 5.5 | ns |
SNR = 80.1 dB, THD = –96.6 dB, ENOB = 12.9 bits |
SNR = 76.8dB, THD = –89.1 dB, fIN = 1000 kHz |
VIN = 0 (differential) |
SNR = 78.7 dB, THD = –89.1 dB, fIN = 500 kHz |
CS = DVDD |
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 32 shows voltage levels for the digital input and output pins.