SBASA78A March 2021 – October 2021 ADS7067
PRODUCTION DATA
Table 7-9 lists the ADS7067 registers. All register offset addresses not listed in Table 7-9 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | SYSTEM_STATUS | #ADS7067_ADS7067_ADS7067_SYSTEM_STATUS | |
0x1 | GENERAL_CFG | #ADS7067_ADS7067_ADS7067_GENERAL_CFG | |
0x2 | DATA_CFG | #ADS7067_ADS7067_ADS7067_DATA_CFG | |
0x3 | OSR_CFG | #ADS7067_ADS7067_ADS7067_OSR_CFG | |
0x4 | OPMODE_CFG | #ADS7067_ADS7067_ADS7067_OPMODE_CFG | |
0x5 | PIN_CFG | #ADS7067_ADS7067_ADS7067_PIN_CFG | |
0x7 | GPIO_CFG | #ADS7067_ADS7067_ADS7067_GPIO_CFG | |
0x9 | GPO_DRIVE_CFG | #ADS7067_ADS7067_ADS7067_GPO_DRIVE_CFG | |
0xB | GPO_OUTPUT_VALUE | #ADS7067_ADS7067_ADS7067_GPO_OUTPUT_VALUE | |
0xD | GPI_VALUE | #ADS7067_ADS7067_ADS7067_GPI_VALUE | |
0x10 | SEQUENCE_CFG | #ADS7067_ADS7067_ADS7067_SEQUENCE_CFG | |
0x11 | CHANNEL_SEL | #ADS7067_ADS7067_ADS7067_CHANNEL_SEL | |
0x12 | AUTO_SEQ_CH_SEL | #ADS7067_ADS7067_ADS7067_AUTO_SEQ_CH_SEL | |
0xBF | DIAGNOSTICS_KEY | #ADS7067_ADS7067_ADS7067_DIAGNOSTICS_KEY | |
0xC0 | DIAGNOSTICS_EN | #ADS7067_ADS7067_ADS7067_DIAGNOSTICS_EN | |
0xC1 | BIT_SAMPLE_LSB | #ADS7067_ADS7067_ADS7067_BIT_SAMPLE_LSB | |
0xC2 | BIT_SAMPLE_MSB | #ADS7067_ADS7067_ADS7067_BIT_SAMPLE_MSB |
Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SYSTEM_STATUS is shown in Figure 7-16 and described in Table 7-11.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | SEQ_STATUS | RESERVED | CRCERR_FUSE | CRCERR_IN | BOR | ||
R-1b | R-0b | R-0b | R-0b | R/W-0b | R/W-1b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSVD | R | 1b | Reads return 1b. |
6 | SEQ_STATUS | R | 0b | Status of the channel sequencer.
0b = Sequence stopped 1b = Sequence in progress |
5-3 | RESERVED | R | 0b | Reserved Bit |
2 | CRCERR_FUSE | R | 0b | Device power-up configuration CRC check status.
To re-evaluate this bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration. 1b = Device configuration not loaded correctly. |
1 | CRCERR_IN | R/W | 0b | Status of CRC check on incoming data.
Write 1b to clear this error flag.
0b = No CRC error. 1b = CRC error detected. All register writes, except to addresses 0x00 and 0x01, are blocked. |
0 | BOR | R/W | 1b | Brown out reset indicator. This bit is set if brown out condition occurs or device is power cycled.
Write 1b to this bit to clear the flag.
0b = No brown out since last time this bit was cleared. 1b = Brown out condition detected or device power cycled. |
GENERAL_CFG is shown in Figure 7-17 and described in Table 7-12.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF_EN | CRC_EN | RESERVED | RANGE | CH_RST | CAL | RST | |
R/W-0b | R/W-0b | R-0b | R/W-0b | R/W-0b | R/W-0b | W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | REF_EN | R/W | 0b | Enable or disable the internal reference.
0b = Internal reference is powered down. 1b = Internal reference is enabled. |
6 | CRC_EN | R/W | 0b | Enable or disable the CRC on device interface.
0b = CRC module disabled. 1b = CRC appended to data output. CRC check is enabled on incoming data. |
5-4 | RESERVED | R | 0b | Reserved Bit |
3 | RANGE | R/W | 0b | Select the input range of the ADC.
0b = Input range of the ADC is 1x VREF 1b = Input range of the ADC is 2x VREF |
2 | CH_RST | R/W | 0b | Force all channels to be analog inputs.
0b = Normal operation 1b = All channels will be set as analog inputs irrespective of configuration in other registers |
1 | CAL | R/W | 0b | Calibrate ADC offset.
0b = Normal operation. 1b = ADC offset is calibrated. After calibration is complete, this bit is set to 0b. |
0 | RST | W | 0b | Software reset all registers to default values.
0b = Normal operation. 1b = Device is reset. After reset is complete, this bit is set to 0b and BOR bit is set to 1b. |
DATA_CFG is shown in Figure 7-18 and described in Table 7-13.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIX_PAT | RESERVED | APPEND_STATUS[1:0] | RESERVED | CPOL_CPHA[1:0] | |||
R/W-0b | R-0b | R/W-0b | R-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FIX_PAT | R/W | 0b | Device outputs fixed data bits which can be helpful for debugging communication with the device.
0b = Normal operation. 1b = Device outputs fixed code 0xA5A5 repeatitively when reading ADC data. |
6 | RESERVED | R | 0b | Reserved Bit |
5-4 | APPEND_STATUS[1:0] | R/W | 0b | Append 4-bit channel ID or status flags to output data.
0b = Channel ID and status flags are not appended to ADC data. 1b = 4-bit channel ID is appended to ADC data. 10b = 4-bit status flags are appended to ADC data. 11b = Reserved. |
3-2 | RESERVED | R | 0b | Reserved Bit |
1-0 | CPOL_CPHA[1:0] | R/W | 0b | This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0. 1b = CPOL = 0, CPHA = 1. 10b = CPOL = 1, CPHA = 0. 11b = CPOL = 1, CPHA = 1. |
OSR_CFG is shown in Figure 7-19 and described in Table 7-14.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OSR[2:0] | ||||||
R-0b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0b | Reserved Bit |
2-0 | OSR[2:0] | R/W | 0b | Selects the oversampling ratio for ADC conversion result.
0b = No averaging 1b = 2 samples 10b = 4 samples 11b = 8 samples 100b = 16 samples 101b = 32 samples 110b = 64 samples 111b = 128 samples |
OPMODE_CFG is shown in Figure 7-20 and described in Table 7-15.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OSC_SEL | CLK_DIV[3:0] | |||||
R-0b | R/W-0b | R/W-1b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0b | Reserved Bit |
4 | OSC_SEL | R/W | 0b | Selects the oscillator for internal timing generation.
0b = High-speed oscillator. 1b = Low-power oscillator. |
3-0 | CLK_DIV[3:0] | R/W | 1b | Sampling speed control when using averaging filters. Refer to section on oscillator and timing control for details. |
PIN_CFG is shown in Figure 7-21 and described in Table 7-16.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIN_CFG[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PIN_CFG[7:0] | R/W | 0b | Configure device channels AIN/GPIO [7:0] as analog inputs or GPIOs.
0b = Channel is configured as analog input. 1b = Channel is configured as GPIO. |
GPIO_CFG is shown in Figure 7-22 and described in Table 7-17.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO_CFG[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPIO_CFG[7:0] | R/W | 0b | Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input. 1b = GPIO is configured as digital output. |
GPO_DRIVE_CFG is shown in Figure 7-23 and described in Table 7-18.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPO_DRIVE_CFG[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPO_DRIVE_CFG[7:0] | R/W | 0b | Configure digital outputs GPO[7:0] as open-drain or push-pull outputs.
0b = Digital output is open-drain; connect external pullup resistor. 1b = Push-pull driver is used for digital output. |
GPO_OUTPUT_VALUE is shown in Figure 7-24 and described in Table 7-19.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPO_OUTPUT_VALUE[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPO_OUTPUT_VALUE[7:0] | R/W | 0b | Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0. 1b = Digital output set to logic 1. |
GPI_VALUE is shown in Figure 7-25 and described in Table 7-20.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPI_VALUE[7:0] | |||||||
R-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPI_VALUE[7:0] | R | 0b | Readback the logic level on GPIO[7:0].
0b = GPIO is at logic 0. 1b = GPIO is at logic 1. |
SEQUENCE_CFG is shown in Figure 7-26 and described in Table 7-21.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ_START | RESERVED | SEQ_MODE[1:0] | ||||
R-0b | R/W-0b | R-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0b | Reserved Bit |
4 | SEQ_START | R/W | 0b | Control for start of channel sequence when using auto sequence mode (SEQ_MODE = 01b).
0b = Stop channel sequencing. 1b = Start channel sequencing in ascending order for channels enabled in AUTO_SEQ_CH_SEL register. |
3-2 | RESERVED | R | 0b | Reserved Bit |
1-0 | SEQ_MODE[1:0] | R/W | 0b | Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID field. 1b = Auto sequence mode; channel selected by AUTO_SEQ_CHSEL. 10b = On-the-fly sequence mode. 11b = Reserved. |
CHANNEL_SEL is shown in Figure 7-27 and described in Table 7-22.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MANUAL_CHID[3:0] | ||||||
R-0b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0b | Reserved Bit |
3-0 | MANUAL_CHID[3:0] | R/W | 0b | In manual mode (SEQ_MODE = 00b), this field contains the 4-bit channel ID of the analog input channel for next ADC conversion. For valid ADC data, the selected channel must not be configured as GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0 1b = AIN1 10b = AIN2 11b = AIN3 100b = AIN4 101b = AIN5 110b = AIN6 111b = AIN7 1000b = Reserved. |
AUTO_SEQ_CH_SEL is shown in Figure 7-28 and described in Table 7-23.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTO_SEQ_CH_SEL[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | AUTO_SEQ_CH_SEL[7:0] | R/W | 0b | Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence. 1b = Analog input channel is enabled in scanning sequence. |
DIAGNOSTICS_KEY is shown in Figure 7-29 and described in Table 7-24.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_KEY[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_KEY[7:0] | R/W | 0b | Enable write access to diagnostics registers in address locations 0xC0, 0xC1, and 0xC2. Write 0x96 to this register to enable write access to diagnostics registers. |
DIAGNOSTICS_EN is shown in Figure 7-30 and described in Table 7-25.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VTEST_EN | RESERVED | BITWALK_EN | ||||
R-0b | R/W-0b | R-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0b | Reserved Bit |
4 | VTEST_EN | R/W | 0b | Enable measurement of internal 1.8 V (typical) test voltage using AIN6. When using this mode, AIN6 pin should not be left floating and should not be connected to any external circuit.
If BITWALK_EN = 1b, this bit has no effect.
0b = Normal operation. 1b = AIN6 is internally connected to 1.8V (typical) test voltage. AIN6 pin should be floating and should not be connected to any external circuit. |
3-1 | RESERVED | R | 0b | Reserved Bit |
0 | BITWALK_EN | R/W | 0b | Enable bit-walk mode of the ADC bit decisions.
0b = Normal operation. 1b = Bit walk mode enabled. |
BIT_SAMPLE_LSB is shown in Figure 7-31 and described in Table 7-26.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BIT_SAMPLE_LSB[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | BIT_SAMPLE_LSB[7:0] | R/W | 0b | Define the [7:0] bit positions during sampling phase of the ADC. This field has no effet when DIAG_EN = 0. |
BIT_SAMPLE_MSB is shown in Figure 7-32 and described in Table 7-27.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BIT_SAMPLE_MSB[7:0] | |||||||
R/W-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | BIT_SAMPLE_MSB[7:0] | R/W | 0b | Define the [15:8] bit positions during sampling phase of the ADC. This field has no effet when DIAG_EN = 0. |