SBASA78B March   2021  – September 2024 ADS7067

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Analog Input and Multiplexer
      2. 6.3.2  Reference
        1. 6.3.2.1 External Reference
        2. 6.3.2.2 Internal Reference
      3. 6.3.3  ADC Transfer Function
      4. 6.3.4  ADC Offset Calibration
      5. 6.3.5  Programmable Averaging Filters
      6. 6.3.6  CRC on Data Interface
      7. 6.3.7  Oscillator and Timing Control
      8. 6.3.8  Diagnostic Modes
        1. 6.3.8.1 Bit-Walk Test Mode
        2. 6.3.8.2 Fixed Voltage Test Mode
      9. 6.3.9  Output Data Format
        1. 6.3.9.1 Status Flags
        2. 6.3.9.2 Output CRC (Device to Host)
        3. 6.3.9.3 Input CRC (Host to Device)
      10. 6.3.10 Device Programming
        1. 6.3.10.1 Enhanced-SPI Interface
        2. 6.3.10.2 Daisy-Chain Mode
        3. 6.3.10.3 Register Read/Write Operation
          1. 6.3.10.3.1 Register Write
          2. 6.3.10.3.2 Register Read
            1. 6.3.10.3.2.1 Register Read With CRC
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Power-Up and Reset
      2. 6.4.2 Manual Mode
      3. 6.4.3 On-the-Fly Mode
      4. 6.4.4 Auto-Sequence Mode
    5. 6.5 ADS7067 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 AVDD and DVDD Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at AVDD = 3V to 5.5V, DVDD = 1.65V to 5.5V, VREF = 2.5V (internal), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
CIN Input capacitance ADC and MUX capacitance 30 pF
DC PERFORMANCE
Resolution No missing codes 16 Bits
DNL Differential nonlinearity –0.75 ±0.4 0.75 LSB
INL Integral nonlinearity –4 ±1 4 LSB
V(OS) Input offset error Post offset calibration, OSR[2:0] = 7 –9 ±0.5 9 LSB
dVOS/dT Input offset thermal drift Post offset calibration, OSR[2:0] = 7 ±0.6 ppm/°C
Offset error match OSR[2:0] = 7 –2.75 0.5 2.75 LSB
GE Gain error(1) External VREF = 2.5 V, OSR[2:0] = 7 –0.06 ±0.01 0.06 %FSR
dGE/dT Gain error thermal drift External VREF = 2.5 V, OSR[2:0] = 7 ±0.5 ppm/°C
Gain error match
OSR[2:0] = 7

 –0.005 ±0.001 0.005 %FSR
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2kHz, VREF = 2.5V (internal) 82.3 85.1 dB
fIN = 2kHz, VREF = 5V, AVDD = 5V 86.7 89.3
SNR Signal-to-noise ratio fIN = 2kHz, VREF = 2.5V (internal) 82.4 85.3 dB
fIN = 2kHz, VREF = 5V, AVDD = 5V 87.7 90
THD Total harmonic distortion fIN = 2kHz –100 dB
SFDR Spurious-free dynamic range fIN = 2kHz 101 dB
Isolation crosstalk fIN = 10kHz –110 dB
REFERENCE
VREF Internal reference output voltage(3) At TA = 25℃ 2.497 2.5 2.503 V
dVREF/dT Internal reference voltage temperature drift 6 19 ppm/°C
CREF Decoupling capacitor at REF pin 1 10 µF
DIGITAL INPUTS
VIL Input low logic level For CS, SCLK, and SDI pins –0.3 0.3 DVDD V
For GPIOX(2) pins –0.3 0.3 AVDD
VIH Input high logic level For CS, SCLK, and SDI pins 0.7 DVDD DVDD V
For GPIOX pins 0.7 AVDD AVDD
DIGITAL OUTPUTS
VOL Output low logic level For SDO pin, IOL = 500µA sink 0 0.2 DVDD V
For GPIOX(2) pins, IOL = 500µA sink 0 0.2 AVDD
VOH Output high logic level For SDO pin, IOH = 500µA source 0.8 DVDD DVDD V
For GPIOX(2) pins, IOH = 500µA source 0.8 AVDD AVDD
POWER SUPPLY
IAVDD Analog supply current AVDD = 3.3V, external reference 1 2 mA
AVDD = 3.3V, internal reference 1.5 2.8
No conversion, external reference 250 µA
No conversion, internal reference 800
IDVDD Digital supply current At full-speed 720 µA
No conversion 32
(1) These specifications include full temperature range variation but not the error contribution from internal reference.
(2) GPIOX refers to GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, and GPIO7 pins.
(3) Does not include the variation in voltage resulting from solder shift effects.