SBAS773A September   2017  – December 2017 ADS7142

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - All Modes
    6. 6.6  Electrical Characteristics - Manual Mode
    7. 6.7  Electrical Characteristics - Autonomous Modes
    8. 6.8  Electrical Characteristics - High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics for All Modes
    12. 6.12 Typical Characteristics for Manual Mode
    13. 6.13 Typical Characteristics for Autonomous Modes
    14. 6.14 Typical Characteristics for High Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  OFFSET Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading data from the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call with Software Reset
        3. 7.3.10.3 General Call with Write Software programmable part of slave address
        4. 7.3.10.4 Configuring Device into High Speed I2C mode
        5. 7.3.10.5 Bus Clear
      11. 7.3.11 Device Programming
        1. 7.3.11.1 Reading Registers
          1. 7.3.11.1.1 Single Register Read
          2. 7.3.11.1.2 Reading a Continuous Block of Registers
        2. 7.3.11.2 Writing Registers
          1. 7.3.11.2.1 Single Register Write
          2. 7.3.11.2.2 Set Bit
          3. 7.3.11.2.3 Clear Bit
          4. 7.3.11.2.4 Writing a continuous block of registers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode with CH0 Only
        2. 7.4.2.2 Manual Mode with AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode with Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode with Pre Alert Data
          2. 7.4.3.1.2 Autonomous Mode with Post Alert Data
        2. 7.4.3.2 Autonomous Mode with Burst Data
          1. 7.4.3.2.1 Autonomous Mode with Start Burst
          2. 7.4.3.2.2 Autonomous Mode with Stop Burst
      4. 7.4.4 High Precision Mode
    5. 7.5 Optimizing Power Consumed by the Device
    6. 7.6 Register Map
      1. 7.6.1 RESET REGISTERS
        1. 7.6.1.1 WKEY Register (address = 17h), [reset = 00h]
        2. 7.6.1.2 DEVICE_RESET Register (address = 14h), [reset = 00h]
      2. 7.6.2 FUNCTIONAL MODE SELECT REGISTERS
        1. 7.6.2.1 OFFSET_CAL Register (address = 15h), [reset = 00h]
        2. 7.6.2.2 OPMODE_SEL Register (address = 1Ch), [reset = 00h]
        3. 7.6.2.3 OPMODE_I2CMODE_STATUS Register (address = 00h), [reset = 00h]
      3. 7.6.3 INPUT CONFIG REGISTER
        1. 7.6.3.1 CHANNEL_INPUT_CFG Register (address = 24h), [reset = 00h]
      4. 7.6.4 ANALOG MUX and SEQUENCER REGISTERS
        1. 7.6.4.1 AUTO_SEQ_CHEN Register (address = 20h), [reset = 03h]
        2. 7.6.4.2 START_SEQUENCE Register (address = 1Eh), [reset = 00h]
        3. 7.6.4.3 ABORT_SEQUENCE Register (address = 1Fh), [reset = 00h]
        4. 7.6.4.4 SEQUENCE_STATUS Register (address = 04h), [reset = 00h]
      5. 7.6.5 OSCILLATOR and TIMING CONTROL REGISTERS
        1. 7.6.5.1 OSC_SEL Register (address = 18h), [reset = 00h]
        2. 7.6.5.2 nCLK_SEL Register (address = 19h), [reset = 00h]
      6. 7.6.6 DATA BUFFER CONTROL REGISTER
        1. 7.6.6.1 DATA_BUFFER_OPMODE Register (address = 2Ch), [reset = 01h]
        2. 7.6.6.2 DOUT_FORMAT_CFG Register (address = 28h), [reset = 00h]
        3. 7.6.6.3 DATA_BUFFER_STATUS Register (address = 01h), [reset = 00h]
      7. 7.6.7 ACCUMULATOR CONTROL REGISTERS
        1. 7.6.7.1 ACC_EN Register (address = 30h), [reset = 00h]
        2. 7.6.7.2 ACC_CH0_LSB Register (address = 08h), [reset = 00h]
        3. 7.6.7.3 ACC_CH0_MSB Register (address = 09h), [reset = 00h]
        4. 7.6.7.4 ACC_CH1_LSB Register (address = 0Ah), [reset = 00h]
        5. 7.6.7.5 ACC_CH1_MSB Register (address = 0Bh), [reset = 00h]
        6. 7.6.7.6 ACCUMULATOR_STATUS Register (address = 02h), [reset = 00h]
      8. 7.6.8 DIGITAL WINDOW COMPARATOR REGISTERS
        1. 7.6.8.1  ALERT_DWC_EN Register (address = 37h), [reset = 00h]
        2. 7.6.8.2  ALERT_CHEN (address = 34h), [reset = 00h]
        3. 7.6.8.3  DWC_HTH_CH0_MSB Register (address = 39h), [reset = 00h]
        4. 7.6.8.4  DWC_HTH_CH0_LSB Register (address = 38h), [reset = 00h]
        5. 7.6.8.5  DWC_LTH_CH0_MSB Register (address = 3Bh), [reset = 00h]
        6. 7.6.8.6  DWC_LTH_CH0_LSB Register (address = 3Ah), [reset = 00h]
        7. 7.6.8.7  DWC_HYS_CH0 (address = 40h), [reset = 00h]
        8. 7.6.8.8  DWC_HTH_CH1_MSB Register (address = 3Dh), [reset = 00h]
        9. 7.6.8.9  DWC_HTH_CH1_LSB Register (address = 3Ch), [reset = 00h]
        10. 7.6.8.10 DWC_LTH_CH1_MSB Register (address = 3Fh), [reset = 00h]
        11. 7.6.8.11 DWC_LTH_CH1_LSB Register (address = 3Eh), [reset = 00h]
        12. 7.6.8.12 DWC_HYS_CH1 (address = 41h), [reset = 00h]
        13. 7.6.8.13 PRE_ALT_MAX_EVENT_COUNT Register (address = 36h), [reset = 00h]
        14. 7.6.8.14 ALERT_TRIG_CHID Register (address = 03h), [reset = 00h]
        15. 7.6.8.15 ALERT_LOW_FLAGS Register (address = 0C), [reset = 00h]
        16. 7.6.8.16 ALERT_HIGH_FLAGS Register (address = 0Eh), [reset = 00h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142 as a Programmable Comparator with False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Higher Power Consumption
          2. 8.2.1.1.2 Fixed Threshold Voltages
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention with Event Counter
          3. 8.2.1.2.3 Fault Diagnostics with Data Buffer
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Event-triggered PIR sensing with ADS7142
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 AVDD and DVDD Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
ADDR to GND –0.3 AVDD + 0.3 V
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP/AIN0 to GND –0.3 AVDD + 0.3 V
AINM/AIN1 to GND –0.3 AVDD + 0.3 V
Input current on any pin except supply pins -10 10 mA
Digital Input to GND –0.3 DVDD + 0.3 V
Storage Temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog Supply Voltage Range 1.65 3.6 V
DVDD Digital Voltage Supply Voltage Range 1.65 3.6 A
TA Ambient temperature –40 125 °C
TJ Junction temperature –60 150 °C

6.4 Thermal Information

THERMAL METRIC(1) ADS7142 UNIT
RUG
10 PINS
RθJA Junction-to-ambient thermal resistance 120.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.7 °C/W
RθJB Junction-to-board thermal resistance 51.1 °C/W
ΨJT Junction-to-top characterization parameter 0.8 °C/W
ΨJB Junction-to-board characterization parameter 51.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics - All Modes

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT - Two-Channel Single-Ended Configuration
Full-scale input voltage span(1) AINP/AIN0 to GND or AINM/AIN1 to GND 0 AVDD V
Absoulte Input voltage range AINP/AIN0 to GND or AINM/AIN1 to GND –0.1 AVDD + 0.1 V
ANALOG INPUT - Single-Channel Single-Ended Configuration (with Remote Ground Sense)
Full-scale input voltage span(1) AINP/AIN0 to GND or AINM/AIN1 to GND 0 AVDD V
Absoulte Input voltage range AINP/AIN0 to GND –0.1 AVDD + 0.1 V
AINM/AIN1 to GND –0.1 0.1 V
ANALOG INPUT - Single-Channel Pseudo-Differential Configuration
Full-scale input voltage span(1) AINP/AIN0 to GND or AINM/AIN1 to GND –AVDD/2 AVDD/2 V
Absoulte Input voltage range AINP/AIN0 to GND –0.1 AVDD + 0.1 V
AINM/AIN1 to GND AVDD/2–0.1 AVDD/2+0.1 V
Internal Oscillator
tHSO Time Period for High Speed Oscillator 50 110 ns
tLPO Time Period for Low Power Oscillator 95.2 300 µs
Digital Input/Output (SCL, SDA)
VIH High Level input Voltage 0.7 × DVDD DVDD V
VIL Low Level input Voltage 0 0.3 × DVDD V
VOL Low Level output Voltage With 3 mA Sink Current and DVDD > 2 V 0 0.4 V
With 3 mA Sink Current and 1.65 V < DVDD < 2 V 0 0.2 × DVDD V
IOL Low Level Output Current (Sink) VOL = 0.4 V for Standard and Fast Mode (100, 400 kHz) 3 mA
VOL = 0.6 V for  Fast Mode (400 kHz) 6
VOL = 0.4 V Fast Mode Plus (1 MHz) 20
IOL Low Level Output Current (Sink) VOL= 0.4 V High Speed (1.7 MHz, 3.4 MHz) 25 mA
II Input Current on Pin 10 µA
CI Input Capacitance on Pin 10 pF
Digital Output (BUSY/RDY)
VOH High Level Output Voltage Isource = 2 mA 0.7 × DVDD DVDD V
VOL High Level Output Voltage Isink = 2 mA 0 0.3 × DVDD V
Digital Output (ALERT)
IOL Low Level Output Current VOL < 0.25 V 5 mA
VOL Low Level Output Voltage Isink = 5 mA 0 0.25 V
POWER-SUPPLY REQUIREMENTS
AVDD Analog Supply Voltage 1.65 3.6 V
DVDD Digital I/O Suplly Voltage 1.65 3.6 V
(1) Ideal Input span, does not include gain or offset error.

6.6 Electrical Characteristics - Manual Mode

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sampling Dynamics
tconv Conversion Time AVDD = 1.65 to 3.6V 1.8 µs
tacq Acquistion Time AVDD = 1.65 to 3.6V 18 TSCL
tcycle Cycle Time AVDD = 1.65 to 3.6V (tconv + tacq) µs
DC Specifications
Resolution 12 Bits
NMC No Missing Codes AVDD = 1.65 to 3.6V 12 Bits
DNL Differential nonlinerity AVDD = 1.65 to 3.6V –0.99 ±0.3 1 LSB(1)
INL Integral nonlinearity –2.75 ±0.5 2.75 LSB
EO Offset Error Post Offset Calibration –2.9 ±0.5 2.9 LSB
dVOS/dT Offset Drift with Temperature Post Offset Calibration 5 ppm/°C
EG Gain Error –0.1 ±0.03 0.1 %FSR
Gain Error Drift with Temperature 5 ppm/°C
AC Specifications
SNR(2) Signal-to-Noise Ratio fin = 2 kHz, AVDD = 3 V, fsample =140 kSPS 68.75 71.4 dB
fin = 2 kHz, AVDD = 1.8 V, fsample =140 kSPS 69.2 dB
THD(2) (3) Total Harmonic Distortion fin = 2 kHz, AVDD = 3 V, fsample =140 kSPS –87.0 dB
fin = 2 kHz, AVDD = 1.8 V, fsample =140 kSPS –84.0 dB
SINAD(2) Signal-to-Noise and distortion fin = 2 kHz, AVDD = 3 V, fsample =140 kSPS 68.5 71.2 dB
fin = 2 kHz, AVDD = 1.8 V, fsample =140 kSPS 69.0 dB
SFDR(2) Spurious Free dynamic range fin = 2 kHz, AVDD = 3 V, fsample =140 kSPS 91.0 dB
BW -3dB Small Signal Bandwidth 25.0 MHz
Power Consumption
IAVDD Analog Supply Current fsample =140 kSPS, SCL = 3.4 MHz 265 300 µA
fsample =5.5 kSPS, SCL = 100 kHz 8 µA
fsample =140 kSPS, SCL = 3.4 MHz, AVDD = 1.8 V 160 µA
fsample =5.5 kSPS, SCL = 100 kHz, AVDD = 1.8 V 5 µA
IDVDD Digital Supply Current fsample =140 kSPS, SCL = 3.4 MHz, SDA = AAA0h 25 µA
fsample =5.5 kSPS, SCL = 100 kHz, AVDD = 1.8 V, SDA = AAA0h 1.5 µA
IAVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 6 nA
IDVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 2 nA
(1) LSB means least significant byte. Refer to ADC Transfer Function for details.
(2) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.
(3) Calculated on the first nine harmonics of the input frequency.

6.7 Electrical Characteristics - Autonomous Modes

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sampling Dynamics
tconv Conversion Time High Speed Oscillator 14 tHSO
Low Power Oscillator 14 tLPO
tacq Acquistion Time High Speed Oscillator 7 tHSO
Low Power Oscillator 4 tLPO
tcycle Cycle Time High Speed Oscillator nCLK tHSO
Low Power Oscillator nCLK tLPO
DC Specifications
Resolution 12 Bits
EO Offset Error Post Offset Calibration ±0.5 LSB
EG Gain Error ±0.03 %FSR
Power Consumption
IAVDD Analog Supply Current With Low Power Oscillator, nCLK =18 0.75 µA
With Low Power Oscillator, AVDD = 1.8 V, nCLK =18 0.45 µA
With Low Power Oscillator, nCLK = 250 0.5 µA
With High Speed Oscillator, nCLK =21 940 µA
IDVDD Digital Supply Current With Low Power Oscillator, nCLK =18, DVDD =3.3 V 0.15 µA
IAVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 5 nA
IDVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 0.6 nA

6.8 Electrical Characteristics - High Precision Mode

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Specifications
Resolution(2) 16 Bits
ENOB Effective number of bits With DC Input of AVDD/2(3) 15.4
EO Offset Error Post Offset Calibration ±10 LSB
EG Gain Error ±0.03 %FSR
Power Consumption
IAVDD Analog Supply Current With Low Power Oscillator, nCLK =18 0.6 µA
With Low Power Oscillator, AVDD = 1.8 V, nCLK =18 0.3 µA
With Low Power Oscillator, nCLK = 250 0.5 µA
With High Speed Oscillator, nCLK =21 980 µA
IDVDD Digital Supply Current With Low Power Oscillator, nCLK =21, DVDD =3.3 V 0.2 µA
IAVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 5 nA
IDVDD Static Analog Supply Current No Activity on SCL and SDA, BUSY/RDY Low 0.7 nA
(1) Sampling Dynamics for High Precision Mode are same as for Autonomous modes.
(2) Refer to Equation 5
(3) For DC Input, ENOB = Ln[FSR/Standard deviation of Codes]/Ln[2]. Refer to Figure 34

6.9 Timing Requirements

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.(1)
PARAMETER Test Conditions MIN MAX UNIT
Standard-mode (100 kHz) Figure 1
fSCL SCL clock frequency 0 100 kHz
tHD-STA Hold time (repeated) START condition After this period, the first clock pulse generated. 4 µs
tLOW Low period of SCL 4.7 µs
tHIGH High period of SCL 4 µs
tSU-STA set-up time for a repeated start condition 4.7 µs
tHD-DAT (2) (3) data hold time For I2C Bus devices 0 µs
tSU-DAT data setup time 250 ns
tSU-STO setup-up time for STOP condition 4 µs
tBUF bus free time between a STOP and START condition 4.7 µs
Cb capacitive load on each line 400 pF
Fast-mode (400 kHz) Figure 1
fSCL SCL clock frequency 0 400 kHz
tHD-STA Hold time (repeated) START condition 0.6 µs
tLOW Low period of SCL 1.3 µs
tHIGH High period of SCL 0.6 µs
tSU-STA set-up time for a repeated start condition 0.6 µs
tHD-DAT data hold time 0 µs
tSU-DAT data setup time 100 ns
tSU-STO setup-up time for STOP condition 0.6 µs
tBUF bus free time between a STOP and START condition 1.3 µs
Cb capacitive load on each line 400 pF
Fast-mode Plus (1000 kHz)  Figure 1
fSCL SCL clock frequency 0 1000 kHz
tHD-STA Hold time (repeated) START condition 0.26 µs
tLOW Low period of SCL 0.5 µs
tHIGH High period of SCL 0.26 µs
tSU-STA set-up time for a repeated start condition 0.26 µs
tHD-DAT data hold time 0 µs
tSU-DAT data setup time 50 ns
tSU-STO setup-up time for STOP condition 0.26 µs
tBUF bus free time between a STOP and START condition 0.5 µs
Cb capacitive load on each line 550 pF
High Speed mode (1.7 MHz) Cb = 400 pF (Max) Figure 2
fSCLH SCLH clock frequency 0 1.7 MHz
tHD-STA Hold time (repeated) START condition 160 ns
tLOW Low period of SCL 320 ns
tHIGH High period of SCL 120 ns
tSU-STA set-up time for a repeated start condition 160 ns
tHD-DAT data hold time 0 150 ns
tSU-DAT data setup time 10 ns
tSU-STO setup-up time for STOP condition 160 ns
Cb capacitive load on each line 400 pF
High Speed mode (3.4 MHz) Cb = 100 pF (Max) Figure 2
fSCLH SCLH clock frequency 0 3.4 MHz
tHD-STA Hold time (repeated) START condition 160 ns
tLOW Low period of SCL 160 ns
tHIGH High period of SCL 60 ns
tSU-STA set-up time for a repeated start condition 160 ns
tHD-DAT data hold time 0 70 ns
tSU-DAT data setup time 10 ns
tSU-STO setup-up time for STOP condition 160 ns
Cb capacitive load on each line 100 pF
(1) All values referred to VIH(min) (0.7 DVDD) and VIL(max) (0.3 DVDD)
(2) tHD-DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
(3) The maximum tHD-DAT could be 3.45 µs and 0.9 µs for Standard-mode and Fast-mode, but must be less than the maximum of tVD-DAT or tVD-ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period  (tLOW) of the SCL signal. If the clock is streched, the data must be valid by the set-up time before it releases.

6.10 Switching Characteristics

At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.(1)
PARAMETER Test Conditions MIN MAX UNIT
Standard-mode (100 kHz) Figure 1
trCL Rise time of SCL 1000 ns
trDA Rise time of SDA 1000 ns
tfCL Fall time of SCL 300 ns
tfDA Fall time of SDA 300 ns
tVD-DAT (2) data valid time 3.45 µs
tVD-ACK (2) data hold time 3.45 µs
Fast-mode (400 kHz) Figure 1
trCL Rise time of SCL 20 300 ns
trDA Rise time of SDA 20 300 ns
tfCL Fall time of SCL 20 × DVDD/3.6 300 ns
tfDA Fall time of SDA 20 × DVDD/3.6 300 ns
tVD-DAT data valid time 0.9 µs
tVD-ACK data hold time 0.9 µs
tSP (3) pulse width of spikes suppressed by the input filter 0 50 ns
Fast-mode Pus (1000 kHz) Figure 1
trCL Rise time of SCL 120 ns
trDA Rise time of SDA 120 ns
tfCL Fall time of SCL 20 × DVDD/3.6 120 ns
tfDA Fall time of SDA 20 × DVDD/3.6 120 ns
tVD-DAT data valid time 0.45 µs
tVD-ACK data hold time 0.45 µs
tSP pulse width of spikes suppressed by the input filter 0 50 ns
High Speed mode (1.7 MHz) Cb = 400 pF (Max) Figure 2
trCL Rise time of SCLH 20 80 ns
trCL1 Rise time of SCLH after a repeated start condition and after an acknowledge bit 20 160 ns
trDA Rise time of SDAH 20 160 ns
tfCL Fall time of SCLH 20 80 ns
tfDA Fall time of SDAH 20 160 ns
tSP pulse width of spikes suppressed by the input filter 0 10 ns
High Speed mode (3.4 MHz) Cb = 100 pF (Max) Figure 2
trCL Rise time of SCLH 10 40 ns
trCL1 Rise time of SCLH after a repeated start condition and after an acknowledge bit 10 80 ns
trDA Rise time of SDAH 10 80 ns
tfCL Fall time of SCLH 10 40 ns
tfDA Fall time of SDAH 10 80 ns
tSP pulse width of spikes suppressed by the input filter 0 10 ns
(1) All values referred to VIH(min) ( 0.7 DVDD ) and VIL(max) ( 0.3 DVDD )
(2) tVD-DAT = time for data signal from SCL LOW to SDA output.
(3) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
ADS7142 Tim_Fs-mode_I2C-bus_BAS773.gif Figure 1. Timing Diagram for Standard-mode, Fast-mode and Fast-mode Plus
ADS7142 Tim_Hs-mode_I2C-bus_BAS773.gif Figure 2. Timing Diagram for High Speed Mode

6.11 Typical Characteristics for All Modes

At TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and Two-Channel, Single-Ended Configuration, unless otherwise noted.
ADS7142 D001_SBAS773.gif
Figure 3. High Speed Oscillator Time Period with Temperature
ADS7142 D002_SBAS773.gif
Figure 4. Low Power Oscillator Time Period with Temperature

6.12 Typical Characteristics for Manual Mode

At TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and Two-Channel, Single-Ended Configuration, unless otherwise noted.
ADS7142 D005_SBAS773.gif
SNR = 69.6 dB THD = -82.9 dB ENOB = 11.2
fsample = 140 kSPS SFDR = 87.2 dB AVDD = 1.8 V
Figure 5. Typical FFT in Manual Mode
ADS7142 D006_SBAS773.gif
SNR = 71.7 dB THD = -85 dB ENOB = 11.5
fsample = 140 kSPS SFDR = 89.2 dB AVDD = 3 V
Figure 6. Typical FFT in Manual Mode
ADS7142 D007_SBAS773.gif
fsample = 140 kSPS
Figure 7. SNR and SINAD in Manual Mode with Temperature
ADS7142 D009_SBAS773.gif
fsample = 140 kSPS
Figure 9. THD in Manual Mode with Temperature
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fsample = 140 kSPS S
Figure 11. THD in Manual Mode with AVDD
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Figure 13. Offset Error in Manual Mode with Temperature
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Figure 15. Gain Error in Manual Mode with Free-Air Temperature
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AVDD = 3 V
Figure 17. Typical DNL in Manual Mode
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AVDD = 3 V
Figure 19. Typical INL in Manual Mode
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Figure 21. DNL in Manual Mode with Temperature
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Figure 23. INL in Manual Mode with Temperature
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fSample = 140 kSPS SCL = 3.4 MHz
Figure 25. IAVDD in Manual Mode with AVDD
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DVDD = 1.8 V
Figure 27. IDVDD in Manual Mode with SCL
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No Activity on SCL and SDA
Figure 29. Static IDVDD in Manual Mode with Temperature
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fsample = 140 kSPS
Figure 8. SNR and SINAD in Manual Mode with AVDD
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fsample = 140 kSPS
Figure 10. SFDR in Manual Mode with Temperature
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Mean code = 2046.9 Standard Deviation = 0.34
Figure 12. Typical DC Code Spread in Manual Mode
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Figure 14. Offset Error in Manual Mode with AVDD
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Figure 16. Gain Error in Manual Mode with AVDD
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AVDD = 1.8 V
Figure 18. Typical DNL in Manual Mode
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AVDD = 1.8 V
Figure 20. Typical INL in Manual Mode
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Figure 22. DNL in Manual Mode with AVDD
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Figure 24. INL in Manual Mode with AVDD
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Figure 26. IAVDD in Manual Mode with Temperature
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No Activity on SCL and SDA
Figure 28. Static IAVDD in Manual Mode with Temperature

6.13 Typical Characteristics for Autonomous Modes

At TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and Two-Channel, Single-Ended Configuration, unless otherwise noted.
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Input Voltage = 1.5 V With High Speed Oscillator
Stop Burst Mode
Figure 30. Analog Input Current in Autonomous modes with nCLK
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Stop Burst Mode With Low Power Oscillator
nCLK = 25
Figure 32. IAVDD in Autonomous Modes with Temperature
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Input Voltage = 1.5 V With Low Power Oscillator
Stop Burst Mode
Figure 31. Analog Input Current in Autonomous modes with nCLK
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Stop Burst Mode With High Speed Oscillator
nCLK = 25
Figure 33. IAVDD in Autonomous Modes with Temperature

6.14 Typical Characteristics for High Precision Mode

At TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and Two-Channel, Single-Ended Configuration, unless otherwise noted.
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Standard Deviation = 1.49 Mean = 32768.5
Figure 34. Typical DC Code Spread in High Precision Mode
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Figure 36. Gain Error in High Precision Mode with Temperature
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With High Speed Oscillator nCLK = 25
Figure 38. IAVDD in High Precision Mode with Temperature
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Figure 35. Offset Error in High Precision Mode with Temperature
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With Low Power Oscillator nCLK = 25
Figure 37. IAVDD in High Precision Mode with Temperature