The ADS7887 device is a 10-bit, 1.25-MSPS, analog-to-digital converter (ADC), and the ADS7888 device is a 8-bit, 1.25-MSPS ADC. These devices include a capacitor-based SAR A/D converter with inherent sample and hold. The serial interface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessors and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output.
The devices operate from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the devices make them suitable for battery-powered applications. The devices also include a power-saving, power-down feature for when the devices are operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other circuit with different supply levels. Also this relaxes restriction on power-up sequencing.
The ADS7887 and ADS7888 are available in 6-pin SOT-23 and SC70 packages and are specified for operation from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS7887 ADS7888 |
SOT-23 (6) | 2.90 mm × 1.60 mm |
SC70 (6) | 2.00 mm × 1.25 mm |
Changes from * Revision (June 2005) to A Revision
PART NUMBER | NAME |
---|---|
SN74LVTH245A | 3.3-V ABT Octal Bus Transceivers With 3-State Outputs |
LMV761 | Low Voltage, Precision Comparator with Push-Pull Output |
TPS54418 | 2.95V to 6V Input, 4A Synchronous Step-Down SWIFT™ Converter |
LMV339 | Quad General Purpose Low-Voltage Comparators |
TPS730 | Low-Noise, High PSRR, RF 200-mA Low-Dropout Linear Regulators |
BIT | < 300 KSPS | 300 KSPS – 1.25 MSPS |
---|---|---|
12-Bit | ADS7866 (1.2 VDD to 3.6 VDD) | ADS7886 (2.35 VDD to 5.25 VDD) |
10-Bit | ADS7867 (1.2 VDD to 3.6 VDD) | ADS7887 (2.35 VDD to 5.25 VDD) |
8-Bit | ADS7868 (1.2 VDD to 3.6 VDD) | ADS7888 (2.35 VDD to 5.25 VDD) |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VDD | — | Power supply input also acts like a reference voltage to ADC. |
2 | GND | — | Ground for power supply, all analog and digital signals are referred with respect to this pin. |
3 | VIN | I | Analog signal input |
4 | SCLK | I | Serial clock |
5 | SDO | O | Serial data out |
6 | CS | I | Chip select signal, active low |
MIN | MAX | UNIT | ||
---|---|---|---|---|
+IN to AGND | –0.3 | VDD + 0.3 | V | |
+VDD to AGND | –0.3 | 7 | V | |
Digital input voltage to GND | –0.3 | 7 | V | |
Digital output to GND | –0.3 | VDD + 0.3 | V | |
Power dissipation, both packages | (TJ(MAX) – TA) / RθJA | |||
Lead temperature, soldering | Vapor phase (60 s) | 215 | °C | |
Infrared (15 s) | 220 | |||
Junction temperature, TJ(MAX) | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADS7887, ADS7888 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23) | DCK (SC70) | |||
6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 114.9 | 150.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.6 | 62.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 36.5 | 43 | °C/W |
ψJT | Junction-to-top characterization parameter | 5.8 | 1.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 36.2 | 42.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input voltage span(1) | 0 | VDD | V | |||
Absolute input voltage range | +IN | –0.2 | VDD + 0.2 | V | ||
Ci | Input capacitance(2) | 21 | pF | |||
IIlkg | Input leakage current | TA = 125°C | 40 | nA | ||
SYSTEM PERFORMANCE | ||||||
Resolution | 10 | Bits | ||||
No missing codes | 10 | Bits | ||||
INL | Integral nonlinearity | –0.75 | ±0.35 | 0.75 | LSB(3) | |
DNL | Differential nonlinearity | –0.5 | ±0.35 | 0.5 | LSB | |
EO | Offset error(4)(5)(6) | –1.5 | ±0.5 | 1.5 | LSB | |
EG | Gain error(5) | –1 | ±0.5 | 1 | LSB | |
SAMPLING DYNAMICS | ||||||
Conversion time | 25-MHz SCLK | 530 | 560 | ns | ||
Acquisition time | 260 | ns | ||||
Maximum throughput rate | 25-MHz SCLK | 1.25 | MHz | |||
Aperture delay | 5 | ns | ||||
Step Response | 160 | ns | ||||
Overvoltage recovery | 160 | ns | ||||
DYNAMIC CHARACTERISTICS | ||||||
THD | Total harmonic distortion(7) | 100 kHz | –84 | –72 | dB | |
SINAD | Signal-to-noise and distortion | 100 kHz | 60.5 | 61 | dB | |
SFDR | Spurious free dynamic range | 100 kHz | 73 | 81 | dB | |
Full power bandwidth | At –3 dB | 15 | MHz | |||
DIGITAL INPUT/OUTPUT | ||||||
VIH | High-level input voltage | VDD = 2.35 V to 5.25 V | VDD – 0.4 | 5.25 | V | |
VIL | Low-level input voltage | VDD = 5 V | 0.8 | V | ||
VDD = 3 V | 0.4 | |||||
VOH | High-level output voltage | At Isource = 200 µA | VDD – 0.2 | V | ||
VOL | Low-level output voltage | At Isink = 200 µA | 0.4 | |||
POWER SUPPLY REQUIREMENTS | ||||||
+VDD | Supply voltage | 2.35 | 3.3 | 5.25 | V | |
Supply current (normal mode) | At VDD = 2.35 V to 5.25 V, 1.25-MHz throughput |
2 | mA | |||
At VDD = 2.35 V to 5.25 V, static state | 1.5 | |||||
Power-down state supply current | SCLK off | 1 | µA | |||
SCLK on (25 MHz) | 200 | |||||
Power dissipation at 1.25-MHz throughput |
VDD = 5 V | 8 | 10 | mW | ||
VDD = 3 V | 3.8 | 6 | ||||
Power dissipation in static state | VDD = 5 V | 5.5 | 7.5 | mW | ||
VDD = 3 V | 3 | 4.5 | ||||
Power-down time | 0.1 | µs | ||||
Power-up time | 0.8 | µs | ||||
Invalid conversions after power up | 1 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input voltage span(1) | 0 | VDD | V | |||
Absolute input voltage range | +IN | –0.2 | VDD + 0.2 | V | ||
Ci | Input capacitance(2) | 21 | pF | |||
IIlkg | Input leakage current | TA = 125°C | 40 | nA | ||
SYSTEM PERFORMANCE | ||||||
Resolution | 8 | Bits | ||||
No missing codes | 8 | Bits | ||||
INL | Integral nonlinearity | –0.3 | ±0.15 | 0.3 | LSB(3) | |
DNL | Differential nonlinearity | –0.3 | ±0.1 | 0.3 | LSB | |
EO | Offset error(4) (5) (6) | –0.5 | ±0.15 | 0.5 | LSB | |
EG | Gain error(5) | –0.5 | ±0.15 | 0.5 | LSB | |
SAMPLING DYNAMICS | ||||||
Conversion time | 25-MHz SCLK | 450 | 480 | ns | ||
Acquisition time | 1.5 MSPS mode, see Figure 34 | 206 | ns | |||
Maximum throughput rate | 25-MHz SCLK | 1.25 | MHz | |||
Aperture delay | 5 | ns | ||||
Step Response | 160 | ns | ||||
Overvoltage recovery | 160 | ns | ||||
DYNAMIC CHARACTERISTICS | ||||||
THD | Total harmonic distortion(7) | 100 kHz | –67.5 | –65 | dB | |
SINAD | Signal-to-noise and distortion | 100 kHz | 49 | 49.5 | dB | |
SFDR | Spurious free dynamic range | 100 kHz | 65 | 77 | dB | |
Full power bandwidth | At –3 dB | 15 | MHz | |||
DIGITAL INPUT/OUTPUT | ||||||
VIH | High-level input voltage | VDD = 2.35 V to 5.25 V | VDD – 0.4 | 5.25 | V | |
VIL | Low-level input voltage | VDD = 5 V | 0.8 | V | ||
VDD = 3 V | 0.4 | |||||
VOH | High-level output voltage | At Isource = 200 µA | VDD – 0.2 | V | ||
VOL | Low-level output voltage | At Isink = 200 µA | 0.4 | |||
POWER SUPPLY REQUIREMENTS | ||||||
+VDD | Supply voltage | 2.35 | 3.3 | 5.25 | V | |
Supply current (normal mode) | At VDD = 2.35 V to 5.25 V, 1.25-MHz throughput | 2 | mA | |||
At VDD = 2.35 V to 5.25 V, static state | 1.5 | |||||
Power-down state supply current | SCLK off | 1 | µA | |||
SCLK on (25 MHz) | 200 | |||||
Power dissipation at 1.25 MHz throughput | VDD = 5 V | 8 | 10 | mW | ||
VDD = 3 V | 3.8 | 6 | ||||
Power dissipation in static state | VDD = 5 V | 5.5 | 7.5 | mW | ||
VDD = 3 V | 3 | 4.5 | ||||
Power-down time | 0.1 | µs | ||||
Power-up time | 0.8 | µs | ||||
Invalid conversions after power up | 1 |
PARAMETER | TEST CONDITIONS(1) | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tconv | Conversion time | ADS7887 | VDD = 3 V | 14 × tSCLK | ns | ||
VDD = 5 V | 14 × tSCLK | ||||||
ADS7888 | VDD = 3 V | 12 × tSCLK | |||||
VDD = 5V | 12 × tSCLK | ||||||
tq | Quiet time | Minimum time required from bus 3-state to start of next conversion | VDD = 3 V | 40 | ns | ||
VDD = 5 V | 40 | ||||||
td1 | Delay time | CS low to first data (0) out | VDD = 3 V | 15 | 25 | ns | |
VDD = 5 V | 13 | 25 | |||||
tsu1 | Setup time | CS low to SCLK low | VDD = 3 V | 10 | ns | ||
VDD = 5 V | 10 | ||||||
td2 | Delay time | SCLK falling to SDO | VDD = 3 V | 15 | 25 | ns | |
VDD = 5 V | 13 | 25 | |||||
th1 | Hold time | SCLK falling to data valid (with 50-pF load) | VDD < 3 V | 7 | ns | ||
VDD > 5 V | 5.5 | ||||||
td3 | Delay time | 16th SCLK falling edge to SDO 3-state | VDD = 3 V | 10 | 25 | ns | |
VDD = 5 V | 8 | 20 | |||||
tw1 | Pulse duration | CS | VDD = 3 V | 25 | 40 | ns | |
VDD = 5 V | 25 | 40 | |||||
td4 | Delay time | CS high to SDO 3-state, see Figure 34 | VDD = 3 V | 17 | 30 | ns | |
VDD = 5 V | 15 | 25 | |||||
twH | Pulse duration | SCLK high | VDD = 3 V | 0.4 × tSCLK | ns | ||
VDD = 5 V | 0.4 × tSCLK | ||||||
twL | Pulse duration | SCLK low | VDD = 3 V | 0.4 × tSCLK | ns | ||
VDD = 5 V | 0.4 × tSCLK | ||||||
Frequency | SCLK | VDD = 3 V | 25 | MHz | |||
VDD = 5 V | 25 | ||||||
td5 | Delay time | Second falling edge of clock and CS to enter in power down (use min spec not to accidently enter in power down, see Figure 35) | VDD = 3 V | –2 | 5 | ns | |
VDD = 5 V | –2 | 5 | |||||
td6 | Delay time | CS and 10th falling edge of clock to enter in power down (use max spec not to accidently enter in power down, see Figure 35) | VDD = 3 V | 2 | –5 | ns | |
VDD = 5 V | 2 | –5 |
The ADS788x devices are ADC converters. The serial interface in each device is controlled by the CS and SCLK signals for easy interface with microprocessors and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output. They both operate in a wide supply range from 2.35 V to 5.25 V and low power consumption makes them suitable for battery-powered applications.
The VIN input to the ADS7887 and ADS7888 must be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer.
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters must be driven with a low impedance source and must be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling capacitor must be placed close to the device. Wide, low impedance traces must be used to connect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from the supply lines. The supply line can be driven by either:
The cycle begins with the falling edge of CS. This point is indicated as a in Figure 32. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by 2 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with two lagging zeros as shown in Figure 32. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 32.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.
The cycle begins with the falling edge of CS . This point is indicated as a in Figure 33. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by 4 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with four lagging zeros as shown in Figure 33. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 11th falling edge. This point is indicated by b in Figure 33.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.
As shown in Figure 34, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at the end of the quiet time (tq) after SDO goes to 3-state.
The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power-down condition as shown in Figure 35.
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For the device to come to the fully powered-up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 36. It is not necessary to continue until the 16th clock if the next conversion starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The primary circuits required to maximize the performance of a high-precision, the successive approximation register (SAR) and analog-to-digital converter (ADC), are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, references the driver circuit, and provides some application circuits designed for the ADS7887 and ADS7888.
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7887 with SNR greater than 61 dB and THD less than –84 dB for input frequencies of 2 kHz to 100 kHz at a throughput of 1.25 MSPS.
To achieve a SINAD of 61 dB, the operational amplifier must have high bandwidth to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 37, OPA365 is selected for its high bandwidth (50 MHz) and low noise (4.5 nV√Hz).
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage internally. The supply to these converters must be driven with a low impedance source and must be decoupled to the ground. To drive supply pin of ADS7887 ultra low noise fast transient response low dropout voltage regulator TPS73201 is selected. Alternatively one can drive supply pin with low impedance voltage reference similar to REF3030.
For a step-by-step design procedure for low power, small form factor digital acquisition (DAQ) circuit based on similar SAR ADCs refer to TI Precision Design, Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor.
SNR: 61.9 dB | THD: –86.8 dB | SINAD: 61.3 dB |
SNR: 61.8 dB | THD: –85.1 dB | SINAD: 61.5 dB |
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage internally. The supply to these converters must be driven with a low impedance source and must be decoupled to the ground Decouple the VDD with 1-µF ceramic decoupling capacitors, as shown in Figure 40. Always set the VDD supply to be greater than or equal to the maximum input signal to avoid saturation of codes.
Figure 43 shows a board layout example for the ADS7887 and ADS7888. Some of the key considerations are:
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
For related documentation see the following:
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
ADS7887 | Click here | Click here | Click here | Click here | Click here |
ADS7888 | Click here | Click here | Click here | Click here | Click here |
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