SLAS605C June   2008  – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Detailed Block Diagram
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSSOP Packages
    2.     Pin Functions: VQFN Packages
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TSSOP
    5. 7.5  Thermal Information: VQFN
    6. 7.6  Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953
    7. 7.7  Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957
    8. 7.8  Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics (All ADS79xx Family Devices)
    11. 7.11 Typical Characteristics (12-Bit Devices Only)
    12. 7.12 Typical Characteristics (12-Bit Devices Only)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Power Saving
    4. 8.4 Device Functional Modes
      1. 8.4.1 Channel Sequencing Modes
      2. 8.4.2 Device Programming and Mode Control
        1. 8.4.2.1 Mode Control Register
        2. 8.4.2.2 Program Registers
      3. 8.4.3 Device Power-Up Sequence
      4. 8.4.4 Operating in Manual Mode
      5. 8.4.5 Operating in Auto-1 Mode
      6. 8.4.6 Operating in Auto-2 Mode
      7. 8.4.7 Continued Operation in a Selected Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Output
      2. 8.5.2 GPIO Registers
      3. 8.5.3 Alarm Thresholds for GPIO Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
    2. 9.2 Typical Applications
      1. 9.2.1 Unbuffered Multiplexer Output (MXO)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 OPA192 Buffered Multiplexer Output (MXO)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
  • DBT|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from B Revision (July 2015) to C Revision

  • Changed 0 to 2.5 V and 0 to 5 V to 0 to VREF and 0 to 2 x VREF in Input Range Features bullet Go
  • Changed GPIO Features bullet Go
  • Changed Optical Line Card Monitoring and Multi-Channel, General-Purpose Signal Monitoring Applications bulletsGo
  • Changed (0 V to 2.5 V and 0 V to 5 V) to (0 V to VREF and 0 V to 2 × VREF) in Description sectionGo
  • Deleted Companion Products tableGo
  • Changed RGE to RHB for two 32-pin VQFN pin diagrams Go
  • Added 30-pin DBT package Go
  • Changed I/O column of Pin Functions: TSSOP Packages table to show full definition instead of abbreviationGo
  • Added active low to definition of CS pin in Pin Functions: TSSOP Packages tableGo
  • Changed pin name and description of Alarm pin in Pin Functions: TSSOP Packages table Go
  • Added settings to description of Range pin in Pin Functions: TSSOP Packages table: added (1) to high and (0) to lowGo
  • Added active low to description of CS pin in Pin Functions: VQFN Packages tableGo
  • Changed pin name and description of Alarm pin in Pin Functions: VQFN Packages table Go
  • Changed value of Input current to any pin except supply pins row from ±10 mA (max) to –10 mA (min) and 10 mA (max) in Absolute Maximum Ratings tableGo
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statementGo
  • Changed minimum specification from –1 LSB to –0.99 LSB in first row of Differential linearity parameterGo
  • Added input to Reference input resistance parameter nameGo
  • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters Go
  • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter Go
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement Go
  • Added input to Reference input resistance parameter name Go
  • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters Go
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement Go
  • Added input to Reference input resistance parameter name Go
  • Changed maximum specification from FF Hex to 255 LSB in Alarm Setting parameters Go
  • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter Go
  • Changed REF and GND pins to REFP and REFM pins in the Reference section Go
  • Added Example Manual Mode Timing Diagram figure and corresponding text to Operating in Manual Mode section Go
  • Added Example Auto-1 Mode Timing Diagram figure and corresponding text to the Operating in Auto-1 Mode section Go
  • Added Example Auto-2 Mode Timing Diagram figure and corresponding text to the Operating in Auto-2 Mode section Go
  • Changed 2.5V to VREF in first DI06 row and 5V to 2xVREF in second DI06 rowGo
  • Changed binary code from 0001 1111 1111 to 0011 1111 1111 in Full scale row of Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) tableGo
  • Changed 10-Bit to 8-Bit in title of Ideal Input Voltages for 8-Bit Devices and Digital Output Codes for 8-Bit Devices (ADS7958/59/60/61) tableGo
  • Changed Application Diagram for an Unbuffered MXO figure note Go
  • Changed Recommended Layout figure title to Recommended Layout for the TSSOP Packaged DeviceGo
  • Added Recommended Layout for the VQFN Packaged Device figureGo

Changes from A Revision (April 2010) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from * Revision (June 2008) to A Revision

  • Added QFN information to FeaturesGo
  • Added QFN information to DescriptionGo
  • Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added terminal functions for QFN packagesGo
  • Changed ADS7950/4/8 QFN package MXO pin from 7 to 3Go
  • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7950/51/52/53Go
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to Absolute input range span range 2 test conditionsGo
  • Added Total unadjusted error (TUE) specificationGo
  • Changed reference voltage at REFP min and max valuesGo
  • Added Note to Electrical Characteristics, ADS7950/51/52/53 Go
  • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7954/55/56/57 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 VGo
  • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 VGo
  • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7958/59/60/61 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 VGo
  • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 VGo
  • Changed tsu1 values from max to minGo
  • Changed tsu2 values from max to minGo
  • Added TOTAL UNADJUSTED ERROR (TUE Max) graphGo
  • Added TOTAL UNADJUSTED ERROR (TUE Min) graphGo
  • Changed GPIO pins descriptionGo
  • Added device powerdown through GPIO in the case of the TSSOP packaged devicesGo
  • Added note to Table 1Go
  • Added note to Table 2Go
  • Added note to Table 5Go
  • Added note to Programming GPIO Registers descriptionGo
  • Added QFN information to Table 11Go
  • Changed DI12 = 1? from No or No to Yes or No in Figure 59Go
  • Added note to Figure 60Go