8.3.2.1 Analog Input: Full-Scale Range Selection

The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). The FSR is given by Equation 1 and Equation 2 :

Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the maximum dynamic range of the ADC can be used.

Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in Equation 3 and Equation 4:

8.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations

The ADS8353, ADS7853, and ADS7253 can support single-ended or pseudo-differential input configurations.

For supporting single-ended inputs, B7 in the configuration register (CFR.B7) must be set to 0 (CFR.B7 = 0) and AINM_A and AINM_B must be externally connected to GND.

For supporting pseudo-differential inputs, CFR.B7 must be set to 1 (CFR.B7 = 1) and AINM_A and AINM_B must be externally connected to FSR_ADC_A / 2 and FSR_ADC_B / 2, respectively. Note that CFR.B7 is common to both ADCs.

The CFR.B9 and CFR.B7 settings can be combined to select the desired input configuration, as shown in Table 1.

Table 1. Input Configurations

INPUT RANGE SELECTION	AINM SELECTION	CONNECTION DIAGRAM
CFR.B9 = 0 (FSR_ADC_A = 0 to VREF_A) (FSR_ADC_B = 0 to VREF_B)	CFR.B7 = 0 (AINM_A = GND) (AINM_B = GND)
CFR.B9 = 1 (FSR_ADC_A = 0 to 2 x VREF_A) (FSR_ADC_B = 0 to 2 x VREF_B)	CFR.B7 = 0 (AINM_A = GND) (AINM_B = GND)
CFR.B9 = 0 (FSR_ADC_A = VREF_A) (FSR_ADC_B = VREF_B)	CFR.B7 = 1 (AINM_A = VREF_A/2) (AINM_B = VREF_B/2)
CFR.B9 = 1 (FSR_ADC_A = 2 x VREF_A) (FSR_ADC_B = 2 x VREF_B)	CFR.B7 = 1 (AINM_A = VREF_A) (AINM_B = VREF_B)

Table 2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)

Table 3. Transfer Characteristics for Twos Compliment Output (CFR.B4 = 1)

Table 4. SCLK Falling Edges for a Valid Write Operation

Table 5. Data Write Operation

8.5.2.1 Configuration Register (CFR)

The device operation configuration is controlled by the configuration register (CFR) status. Data written into the CFR in a valid frame (F) determine the device configuration for frame (F+1). The bit functions are outlined in Figure 88. On power-up, all bits in the CFR default to 0.

8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)

The REFDAC registers, bit functions, and resolution information are described in this section.

8.5.3.1 Reading User-Programmable Registers

The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B. Figure 90 shows a detailed timing diagram for this operation.

Note that N is a function of the device configuration, as described in Table 4.

Figure 90. Register Readback Timing

To readback the user-programmable register settings, the appropriate control word should be transmitted to the device during frame (F+1), as shown in Table 9. Frame (F+1) must have at least 48 SCLK falling edges.

Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 10) and then outputs 0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.

Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).

8.5.3.2 Conversion Data Read

The device provides four different interface modes to the user for reading the conversion result. These modes offer flexible hardware connections and firmware programming. Table 11 shows how to select one of the four interface modes.

In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the subsequent SCLK falling edges. All devices in the family (that is, ADS8353, ADS7853, and ADS7253) support the 32-CLK interface modes.

In addition to the 32-CLK interface modes, the ADS7853 and ADS7253 also support the 16-CLK interface modes. By using the 16-CLK interface modes, the same throughput can be achieved at much lower SCLK speeds.

The following sections detail the various interface modes supported by the device.

8.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)

The 32-CLK, dual-SDO mode is the default mode supported by all devices. This mode can also be selected by writing CFR.B11 = 0 and CFR.B10 = 0.

In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 91 shows a detailed timing diagram for this mode.

Figure 91. 32-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The device converts the sampled analog input during the conversion time (t_CONV). SDO_A and SDO_B read 0 during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. The device outputs the MSBs of ADC_A and ADC_B on SDO_A and SDO_B pins, respectively, on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion result, as shown in Table 12.

Table 12. Data Launch Edge

DEVICE	PINS	LAUNCH EDGE
		CS	SCLK											CS
		↓	↓1	—	↓15	↓16	—	↓27	↓28	↓29	↓30	↓31	↓32 ...	↑
ADS8353	SDO-A	0	0	—	0	D15_A	—	D4_A	D3_A	D2_A	D1_A	D0_A	0 ...	Hi-Z
	SDO-B	0	0	—	0	D15_B	—	D4_B	D3_B	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7853	SDO-A	0	0	—	0	D13_A	—	D2_A	D1_A	D0_A	0	0	0 ...	Hi-Z
	SDO-B	0	0	—	0	D13_B	—	D2_B	D1_B	D0_B	0	0	0 ...	Hi-Z
ADS7253	SDO-A	0	0	—	0	D11_A	—	D0_A	0	0	0	0	0 ...	Hi-Z
	SDO-B	0	0	—	0	D11_B	—	D0_B	0	0	0	0	0 ...	Hi-Z

In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 13 for timing specifications specific to this serial interface mode.

Table 13. 32-CLK, Dual-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
tCLK	CLOCK period	ADS8353	50			ns
		ADS7853	29.4			ns
		ADS7253	29.4			ns
tACQ	Acquisition time			33 × tCLK – tCONV		ns
TIMING SPECIFICATIONS
tCONV	Conversion time	ADS8353			730	ns
		ADS7853			450	ns
		ADS7253			450	ns

8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)

The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect (NC) pin.

This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 92 shows a detailed timing diagram for this mode.

Figure 92. 32-CLK, Single-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device converts the sampled analog input during the conversion time (t_CONV). SDO_A reads 0 during this period. After competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin, as shown in Table 14.

Table 14. Data Launch Edge

DEVICE	PIN	LAUNCH EDGE
		CS	SCLK																		CS
		↓	↓1	—	↓15	↓16	—	↓27	↓28	↓29	↓30	↓31	↓32	—	↓43	↓44	↓45	↓46	↓47	↓48 ...	↑
ADS8353	SDO-A	0	0	—	0	D15_A	—	D4_A	D3_A	D2_A	D1_A	D0_A	D15_B	—	D4_B	D3_B	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7853	SDO-A	0	0	—	0	D13_A	—	D2_A	D1_A	D0_A	0	0	0	—	D2_B	D1_B	D0_B	0	0	0 ...	Hi-Z
ADS7253	SDO-A	0	0	—	0	D11_A	—	D0_A	0	0	0	0	0	—	D0_B	0	0	0	0	0 ...	Hi-Z

In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 15 for timing specifications specific to this serial interface mode.

Table 15. 32-CLK, Single-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
tCLK	CLOCK period	ADS8353	50			ns
		ADS7853	29.4			ns
		ADS7253	29.4			ns
tACQ	Acquisition time			49 × tCLK – tCONV		ns
TIMING SPECIFICATIONS
tCONV	Conversion time	ADS8353			730	ns
		ADS7853			450	ns
		ADS7253			450	ns

8.5.3.2.3 16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)

The 16-CLK, dual-SDO mode is designed to support the maximum throughput at lower SCLK frequencies. This interface mode is not supported by the ADS8353.

For the ADS7853 and ADS7253, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0. In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 93 shows a detailed timing diagram for this mode.

Figure 93. 16-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown in Table 16.

The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.

Table 16. Data Launch Edge

DEVICE	PINS	LAUNCH EDGE
		CS	SCLK							CS
		↓	↓1	↓2	—	↓13	↓14	↓15	↓16 ...	↑
ADS7853	SDO-A	0	0	D13_A	—	D2_A	D1_A	D0_A	0 ...	Hi-Z
	SDO-B	0	0	D13_B	—	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7253	SDO-A	0	0	D11_A	—	D0_A	0	0	0 ...	Hi-Z
	SDO-B	0	0	D11_B	—	D0_B	0	0	0 ...	Hi-Z

In this mode, at least 16 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 17 for timing specifications specific to this serial interface mode.

Table 17. 16-CLK, Dual-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
tCLK	CLOCK period	ADS7853	55.5			ns
		ADS7253	55.5			ns
tACQ	Acquisition time	ADS7853		4 × tCLK		ns
		ADS7253		6 × tCLK		ns
TIMING SPECIFICATIONS
tCONV	Conversion time	ADS7853		14 × tCLK		ns
		ADS7253		12 × tCLK		ns

8.5.3.2.4 16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)

The 16-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) and a lower-speed clock to read the conversion results of both ADCs. This interface mode is not supported by the ADS8353.

For the ADS7853 and ADS7253, this mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 1. The SDO_A pin is used to output the conversion results of both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect (NC) pin. Figure 94 shows a detailed timing diagram for this mode.

Figure 94. 16-CLK, Single-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown in Table 18.

The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.

Table 18. Data Launch Edge

DEVICE	PIN	LAUNCH EDGE
		CS	SCLK														CS
		↓	↓1	↓2	—	↓13	↓14	↓15	↓16	↓17	↓18	—	↓29	↓30	↓31	↓32 ...	↑
ADS7853	SDO-A	0	0	D13_A	—	D2_A	D1_A	D0_A	0	0	D13_B	—	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7253	SDO-A	0	0	D11_A	—	D0_A	0	0	0	0	D11_B	—	D0_B	0	0	0 ...	Hi-Z

In this mode, at least 32 SCLK falling edges must be given to validate the read/write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 19 for timing specifications specific to this serial interface mode.

Table 19. 16-CLK, Single-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
tCLK	CLOCK period	ADS7853	55.5			ns
		ADS7253	55.5			ns
tACQ	Acquisition time	ADS7853		19 × tCLK		ns
		ADS7253		21 × tCLK		ns
TIMING SPECIFICATIONS
tCONV	Conversion time	ADS7853		14 × tCLK		ns
		ADS7253		12 × tCLK		ns

8.5.4.1 STANDBY Mode

The device supports a STANDBY mode of operation where some of the internal circuits of the device are powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster power-up to a normal mode of operation.

As shown in Figure 95, a valid write operation in frame (F) to program the configuration register with B5 set to 1 (CFR.B5 = 1) places the device into a STANDBY mode of operation on the following CS rising edge. While in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.

To remain in STANDBY mode, SDI must remain low in the subsequent frames.

Note that N is a function of the device configuration, as described in Table 4.

Figure 95. Enter STANDBY Mode

As shown in Figure 96, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0 (CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have at least 48 SCLK falling edges.

After exiting the STANDBY mode, a delay of t_{PU_STDBY} must elapse for the internal circuits to fully power-up and resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the CFR.B[11:6] bits programmed during frame (F+3).

Note that N is a function of the device configuration, as described in Table 4.

Figure 96. Exit STANDBY Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

8.5.4.2 Software Power-Down (SPD) Mode

In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down. However, the contents of the REFDAC_A and REFDAC_B registers are retained.

As shown in Figure 97, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS signal.

To remain in SPD mode, SDI must remain high in subsequent frames.

Figure 97. Enter SPD Mode

As shown in Figure 98, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising edge following frame (F+3). After frame (F+3), a delay of t_{PU_SPD} must elapse before programming the configuration register.

A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at least 48 SCLK falling edges. The output data in frame (F+4) should be discarded.

Note that N is a function of the device configuration, as described in Table 4.

Figure 98. Exit SPD Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.