7.6.1.1 PD_STANDBY Register (Offset = 4h) [reset = 0h]
PD_STANDBY is shown in Figure 33 and described in Table 9.
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Power down configuration register
Figure 33. PD_STANDBY Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
STANDBY |
PD_EN |
RESERVED |
R-00000b |
R/W-0b |
R/W-0b |
R-0b |
|
Table 9. PD_STANDBY Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
00000b |
|
2 |
STANDBY |
R/W |
0b |
This bit enables partial powerdown of ADCs and internal oscillator , all other blocks are active
0b = Disable partial power down
1b = Enable partial power down
|
1 |
PD_EN |
R/W |
0b |
This bit enables all blocks to powerdown except the interface and IO
0b = Disable power down
1b = Enable power down
|
0 |
RESERVED |
R |
0b |
|