7.6.1.3 SDO_CTRL Register (Offset = Dh) [reset = 0h]
SDO_CTRL is shown in Figure 35 and described in Table 11.
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SDO mode selection register
Figure 35. SDO_CTRL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
SDO_MODE |
R-0000000b |
R/W-0b |
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Table 11. SDO_CTRL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-1 |
RESERVED |
R |
0000000b |
|
0 |
SDO_MODE |
R/W |
0b |
This bit selects ADC to output data in either single SDO or Dual SDO mode.
0b = data out on both SDO_A and SDO_B
1b = data out on SDO_A only
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