SBAS543C August   2011  – February 2016 ADS8528 , ADS8548 , ADS8568

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8528
    7. 7.7  Electrical Characteristics: ADS8548
    8. 7.8  Electrical Characteristics: ADS8568
    9. 7.9  Serial Interface Timing Requirements
    10. 7.10 Parallel Interface Timing Requirements (Read Access)
    11. 7.11 Parallel Interface Timing Requirements (Write Access)
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog
        1. 9.3.1.1 Analog Inputs
        2. 9.3.1.2 Analog-to-Digital Converter (ADC)
        3. 9.3.1.3 Conversion Clock
        4. 9.3.1.4 CONVST_x
        5. 9.3.1.5 Data Readout and BUSY/INT Signal
        6. 9.3.1.6 Sequential Operation
        7. 9.3.1.7 Reference
      2. 9.3.2 Digital
        1. 9.3.2.1 Device Configuration
        2. 9.3.2.2 Parallel Interface
        3. 9.3.2.3 Serial Interface
        4. 9.3.2.4 Output Data Format
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Mode
      2. 9.4.2 Software Mode
      3. 9.4.3 Daisy-Chain Mode
      4. 9.4.4 Reset and Power-Down Modes
    5. 9.5 Register Maps
      1. 9.5.1 Configuration (CONFIG) Register
        1. 9.5.1.1 CONFIG: Configuration Register (default = 000003FFh)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

The ADS85x8 require four separate supplies: an analog supply for the ADC (AVDD), the buffer I/O supply for the digital interface (DVDD), and the two high-voltage supplies driving the analog input circuitry (HVDD and HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device. However, when HVDD is supplied before AVDD, the internal electrostatic discharge (ESD) structure conducts, increasing the IHVDD beyond the specified value until AVDD is applied.

The AVDD supply provides power to the internal circuitry of the ADC. If run at maximum data rate, the IAVDD is too high to allow use of a passive filter between the digital board supply of the application and the AVDD pins. A linear regulator is recommended to generate the analog supply voltage. Decouple each AVDD pin to AGND with a 100-nF ceramic capacitor. In addition, place a single 10-µF capacitor close to the device but without compromising the placement of the smaller capacitors. Optionally, each supply pin can be decoupled using a
1-µF ceramic capacitor without the requirement of the additional 10-µF capacitor.

The DVDD supply is only used to drive the digital I/O buffers and allows seamless interface with most state-of-the-art processors and controllers. Resulting from the low IDVDD value, a 10-Ω series resistor can be used on the DVDD pin to reduce the noise energy from the external digital circuitry influencing the performance of the device. Place a 1-µF bypass ceramic capacitor (or alternatively, a pair of 100-nF and 10-µF capacitors) between pins 24 and 25.

The high-voltage supplies (HVSS and HVDD) are connected to the analog inputs. These supplies are not required to be of symmetrical nature with regard to AGND. Noise and glitches on these supplies directly couple into the input signals. Place a 100-nF ceramic decoupling capacitor, located as close to the device as possible, between pins 1, 48, and AGND. An additional 10-µF capacitor is used that must be placed close to the device but without compromising the placement of the smaller capacitors.