SBAS843A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Timing Diagrams
    21. 6.21 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUTS
Full-scale input span(1)
(AIN_nP to AIN_nGND)		RANGE pin = 1–1010V
RANGE pin = 0–55
AIN_nPOperating input range,
positive input		RANGE pin = 1–1010V
RANGE pin = 0–55
AIN_nGNDOperating input range,
negative input		RANGE pin = 1–0.300.3V
RANGE pin = 0–0.300.3
RINInput impedanceAt TA = 25°C0.8511.15MΩ
Input impedance driftAll input ranges–25±725ppm/°C
IIkg(in)Input leakage currentWith voltage at AIN_nP = VIN,
all input ranges		(VIN – 2) / RINµA
SYSTEM PERFORMANCE
Resolution16Bits
NMCNo missing codes16Bits
DNLDifferential nonlinearityAll input ranges–0.6±0.30.6LSB(2)
INLIntegral nonlinearity(5)All input ranges–1.5±0.51.5LSB
EGGain error(9)All input ranges,
external reference		TA = –40°C to +85°C–64±464LSB
TA = –40°C to +125°C–64±496
All input ranges,
internal reference		±4
Gain error matching
(channel-to-channel)		Input range = ±10 V,
external and internal reference		1060LSB
Input range = ±5 V,
external and internal reference		1260
Gain error temperature driftAll input ranges,
external reference		–14±614ppm/°C
All input ranges,
internal reference		±10
EOOffset errorInput range = ±10 V–3±0.23mV
Input range = ±5 V–3±0.153
Offset error matching
(channel-to-channel)		All input ranges0.75mV
Offset error temperature driftAll input ranges–3±0.33ppm/°C
SAMPLING DYNAMICS
tACQAcquisition time0.7µs
fSMaximum throughput rate per channel without latencyAll eight channels included500kSPS
DYNAMIC CHARACTERISTICS
SNRSignal-to-noise ratio(3),
no oversampling
(VIN – 0.5 dBFS at 1 kHz)		Input range = ±10 V9192.7dB
Input range = ±5 V89.592.1
SNROSRSignal-to-noise ratio(3),
oversampling = 32x
(VIN – 0.5 dBFS at 130 Hz)		Input range = ±10 V95.596.9dB
Input range = ±5 V9495.8
THDTotal harmonic distortion(3)(4)
(VIN – 0.5 dBFS at 1 kHz)		All input ranges–110–95dB
SINADSignal-to-noise + distortion ratio(3),
no oversampling
(VIN – 0.5 dBFS at 1 kHz)		Input range = ±10 V90.992.6dB
Input range = ±5 V89.292
SINADOSRSignal-to-noise + distortion ratio(3),
oversampling = 16 x
(VIN – 0.5 dBFS at 130 Hz)		Input range = ±10 V94.7596.5dB
Input range = ±5 V93.595.3
SFDRSpurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)		All input ranges110dB
Crosstalk isolation(6)–95dB
BW(–3 dB)Small-signal bandwidth, –3 dBAt TA = 25°C,
input range = ±10 V		24kHz
At TA = 25°C,
input range = ±5 V		16
BW(–0.1 dB)Small-signal bandwidth, –0.1 dBAt TA = 25°C,
input range = ±10 V		14kHz
At TA = 25°C,
input range = ±5 V		9.5
tGROUPGroup delayInput range = ±10 V13µs
Input range = ±5 V19
INTERNAL REFERENCE OUTPUT (REFSEL = 1)
VREF(7)Voltage on the REFIN/REFOUT pin
(configured as output)		At TA = 25°C2.49752.52.5025V
Internal reference temperature drift7.5ppm/°C
C(REFIN_ REFOUT)Decoupling capacitor on REFIN/REFOUT(8)10µF
V(REFCAP)Reference voltage to the ADC
(on the REFCAPA, REFCAPB pin)		At TA = 25°C3.9964.04.004V
Reference buffer output impedance0.51Ω
Reference buffer output temperature drift5ppm/°C
C(REFCAP)Decoupling capacitor on REFCAPA, REFCAPB10µF
Turn-on timeC(REFCAP) = 10 µF,
C(REFIN_REFOUT) = 10 µF		25ms
EXTERNAL REFERENCE INPUT (REFSEL = 0)
VREFIO_EXTExternal reference voltage on REFIO
(configured as input)		2.4752.52.525V
Reference input impedance100MΩ
Reference input capacitance10pF
POWER-SUPPLY REQUIREMENTS
AVDDAnalog power-supply voltageAnalog supply4.7555.25V
DVDDDigital power-supply voltageDigital supply range2.33.3AVDDV
IAVDD_DYNAnalog supply current
(operational)		AVDD = 5 V,
fS = 500 kSPS,
internal reference		22.830.8mA
AVDD = 5 V,
fS = 500 kSPS,
external reference		22.230
IAVDD_STCAnalog supply current
(static)		AVDD = 5 V, internal reference,
device not converting		12.717.4mA
AVDD = 5 V, external reference,
device not converting		12.316.7
IAVDD_STDBYAVDD supply
STANDBY current		At AVDD = 5 V, device in STDBY mode,
internal reference		4.25.5mA
At AVDD = 5 V, device in STDBY mode,
external reference		3.85
IAVDD_PWR_ DNAVDD supply
power-down current		At AVDD = 5 V, device in PWR_DN, internal or
external reference,
TA = –40°C to +85°C		0.26µA
IDVDD_DYNDigital supply currentDVDD = 3.3 V, fS = 500 kSPS0.20.33mA
IDVDD_STDBYDVDD supply STANDBY currentAt AVDD = 5 V, device in STDBY mode0.051.5µA
IDVDD_PWR-DNDVDD supply power-down currentAt AVDD = 5 V, device in PWR_DN mode0.051.5µA
DIGITAL INPUTS (CMOS)
VIHDigital high input voltage logic levelDVDD > 2.3 V0.8 × DVDDDVDD + 0.3V
VILDigital low input voltage logic levelDVDD > 2.3 V–0.30.2 × DVDDV
Input leakage current100nA
Input pin capacitance5pF
DIGITAL OUTPUTS (CMOS)
VOHDigital high output voltage logic levelIO = 100-µA source0.8 × DVDDDVDDV
VOLDigital low output voltage logic levelIO = 100-µA sink00.2 × DVDDV
Floating state leakage currentOnly for SDO1µA
Internal pin capacitance5pF
TEMPERATURE RANGE
TAOperating free-air temperature–40125°C
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit.
(3) Device specifications are dependent on input ranges, irrespective of whether programming is done by pins or SPI registers.
(4) Calculated on the first nine harmonics of the input frequency.
(5) This parameter is the endpoint INL, not best-fit INL.
(6) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel.
(7) Does not include the variation in voltage resulting from solder shift effects.
(8) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).
(9) Gain error is calculated after adjusting for offset error, which implies that the positive full-scale error = negative full-scale error = gain error ÷ 2.