SBAS843A september 2017 – july 2023 ADS8588H
PRODUCTION DATA
RD/SCLK is a dual-function pin. Table 7-4 explains the usage of this pin under different operating conditions of the device.
DEVICE OPERATING CONDITION | FUNCTIONALITY OF THE RD/SCLK INPUT | |
---|---|---|
MODE | CONDITIONS | |
Parallel interface | PAR/SER/BYTE SEL = 0 DB15/BYTE SEL = X |
Functions as an active-low digital input pin to read the output data from the device. In parallel or parallel byte interface mode, the output bus is enabled when both the CS and RD inputs are tied to a logic low input (see the Data Read Operation section). |
Parallel byte interface | PAR/SER/BYTE SEL = 1 DB15/BYTE SEL = 1 |
|
Serial interface | PAR/SER/BYTE SEL = 1 DB15/BYTE SEL = 0 |
Functions as an external clock input for the serial data interface. In serial mode, all synchronous accesses to the device are timed with respect to the rising edge of the SCLK signal (see the Serial Data Read section). |