SBAS829 September   2017 ADS8598H

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8598H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Extending the Analog Input Voltage Range
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Performance Results
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

at TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
AVDD to AGND –0.3 7.0 V
DVDD to AGND –0.3 7.0 V
Analog input voltage to AGND(2) –15 15 V
Digital input to AGND –0.3 DVDD + 0.3 V
REFIN to AGND –0.3 AVDD + 0.3 V
Input current to any pin except supplies(2) –10 10 mA
Temperature Operating –40 125 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient currents of up to 100 mA do not cause SCR latch-up.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM),
per ANSI/ESDA/JEDEC JS-001(1)		 All pins except analog inputs ±2000 V
Analog input pins only ±9000
Charged-device model (CDM),
per JEDEC specification JESD22-C101(2)		 ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 4.75 5 5.25 V
DVDD Digital supply voltage 2.3 3.3 AVDD V

6.4 Thermal Information

THERMAL METRIC(1) ADS8598H UNIT
PM (LQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 46.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 7.8 °C/W
RθJB Junction-to-board thermal resistance 20.1 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 19.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input span(1)
(AIN_nP to AIN_nGND)		 RANGE pin = 1 –10 10 V
RANGE pin = 0 –5 5
AIN_nP Operating input range,
positive input		 RANGE pin = 1 –10 10 V
RANGE pin = 0 –5 5
AIN_nGND Operating input range,
negative input		 All input ranges –0.3 0 0.3 V
RIN Input impedance At TA = 25°C 0.85 1 1.15 MΩ
Input impedance drift All input ranges –25 ±7 25 ppm/°C
IIkg(in) Input leakage current With voltage at AIN_nP = VIN,
all input ranges		 (VIN – 2) / RIN µA
SYSTEM PERFORMANCE
Resolution 18 Bits
NMC No missing codes 18 Bits
DNL Differential nonlinearity All input ranges –0.9 ±0.5 0.9 LSB(2)
INL Integral nonlinearity(4) All input ranges –5.5 ±2.5 5.5 LSB
EG Gain error(8) All input ranges,
external reference		 TA = –40°C to +85°C –256 ±16 256 LSB
TA = –40°C to +125°C –256 ±16 300
All input ranges,
internal reference		 ±16
Gain error matching
(channel-to-channel)		 Input range = ±10 V,
external and internal reference		 32 170 LSB
Input range = ±5 V,
external and internal reference		 34 170
Gain error temperature drift All input ranges,
external reference		 –14 ±6 14 ppm/°C
All input ranges,
internal reference		 ±10
EO Offset error Input range = ±10 V –3 ±0.3 3 mV
Input range = ±5 V –3 ±0.3 3
Offset error matching
(channel-to-channel)		 All input ranges 0.75 5 mV
Offset error temperature drift All input ranges –3 ±0.3 3 ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time 0.7 µs
fS Maximum throughput rate per channel without latency All eight channels included 500 kSPS
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio,
no oversampling
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±10 V 92 94 dB
Input range = ±5 V 90.25 93.2
SNROSR Signal-to-noise ratio,
oversampling = 32x
(VIN – 0.5 dBFS at 130 Hz)		 Input range = ±10 V 99.1 101.9 dB
Input range = ±5 V 96.4 98.8
THD Total harmonic distortion(3)
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges –107 –95 dB
SINAD Signal-to-noise + distortion ratio,
no oversampling
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±10 V 91.7 93.9 dB
Input range = ±5 V 90 93.1
SINADOSR Signal-to-noise + distortion ratio,
oversampling = 32x
(VIN – 0.5 dBFS at 130 Hz)		 Input range = ±10 V 97.6 101 dB
Input range = ±5 V 95.6 98.2
SFDR Spurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges 109 dB
Crosstalk isolation(5) –95 dB
BW(–3 dB) Small-signal bandwidth, –3 dB At TA = 25°C,
input range = ±10 V		 24 kHz
At TA = 25°C,
input range = ±5 V		 16
BW(–0.1 dB) Small-signal bandwidth, –0.1 dB At TA = 25°C,
input range = ±10 V		 14 kHz
At TA = 25°C,
input range = ±5 V		 9.5
tGROUP Group delay Input range = ±10 V 13 µs
Input range = ±5 V 19
INTERNAL REFERENCE OUTPUT (REFSEL = 1)
VREF(6) Voltage on the REFIN/REFOUT pin
(configured as output)		 At TA = 25°C 2.4975 2.5 2.5025 V
Internal reference temperature drift 7.5 ppm/°C
C(REFIN_ REFOUT) Decoupling capacitor on the REFIN/REFOUT pin(7) 10 µF
V(REFCAP) Reference voltage to the ADC
(on the REFCAPA, REFCAPB pin)		 At TA = 25°C 3.996 4.0 4.004 V
Reference buffer output impedance 0.5 1 Ω
Reference buffer output temperature drift 5 ppm/°C
C(REFCAP) Decoupling capacitor on REFCAPA, REFCAPB 10 µF
Turn-on time C(REFCAP) = 10 µF,
C(REFIN_REFOUT) = 10 µF		 25 ms
EXTERNAL REFERENCE INPUT (REFSEL = 0)
VREFIO_EXT External reference voltage on REFIO
(configured as input)		 2.475 2.5 2.525 V
Reference input impedance 100 MΩ
Reference input capacitance 10 pF
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V
DVDD Digital power-supply voltage Digital supply range 2.3 3.3 AVDD V
IAVDD_DYN Analog supply current
(operational)		 AVDD = 5 V,
fS = 500 kSPS,
internal reference		 22.8 30.8 mA
AVDD = 5 V,
fS = 500 kSPS,
external reference		 22.2 30.0
IAVDD_STC Analog supply current
(static)		 AVDD = 5 V, internal reference,
device not converting		 12.7 17.4 mA
AVDD = 5 V, external reference,
device not converting		 12.3 16.7
IAVDD_STDBY AVDD supply
STANDBY current		 At AVDD = 5 V, device in STDBY mode, internal reference 4.2 5.5 mA
At AVDD = 5 V, device in STDBY mode, external reference 3.8 5.0
IAVDD_PWR_ DN AVDD supply
power-down current		 At AVDD = 5 V, device in PWR_DN, internal or
external reference,
TA = –40°C to +85°C		 0.2 6 µA
IDVDD_DYN Digital supply current DVDD = 3.3 V,
fS = 500 kSPS		 0.2 0.33 mA
IDVDD_STDBY DVDD supply STANDBY current At AVDD = 5 V, device in STDBY mode 0.05 1.5 µA
IDVDD_PWR-DN DVDD supply power-down current At AVDD = 5 V, device in PWR_DN mode 0.05 1.5 µA
DIGITAL INPUTS (CMOS)
VIH Digital high input voltage logic level DVDD > 2.3 V 0.8 × DVDD DVDD + 0.3 V
VIL Digital low input voltage logic level DVDD > 2.3 V –0.3 0.2 × DVDD V
Input leakage current 100 nA
Input pin capacitance 5 pF
DIGITAL OUTPUTS (CMOS)
VOH Digital high output voltage logic level IO = 100-µA source 0.8 × DVDD DVDD V
VOL Digital low output voltage logic level IO = 100-µA sink 0 0.2 × DVDD V
Floating state leakage current Only for SDO 1 µA
Internal pin capacitance 5 pF
TEMPERATURE RANGE
TA Operating free-air temperature –40 125 °C
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit.
(3) Calculated on the first nine harmonics of the input frequency.
(4) This parameter is the endpoint INL, not best-fit INL.
(5) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel.
(6) Does not include the variation in voltage resulting from solder shift effects.
(7) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).
(8) Gain error is calculated after adjusting for offset error, which implies that positive full scale error = negative full scale error = gain error ÷ 2.

6.6 Timing Requirements: CONVST Control

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 1)
MIN NOM MAX UNIT
tACQ Acquisition time:
BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB		 0.7 µs
tPH_CN CONVSTA, CONVSTB pulse high time 25 ns
tPL_CN CONVSTA, CONVSTB pulse low time 25 ns
tSU_BSYCS Setup time: BUSY falling to CS falling 0 ns
tSU_RSTCN Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB 25 ns
tPH_RST RESET pulse high time 50 ns
tD_CNAB Delay between rising edges of CONVSTA and CONVSTB 500 µs

6.7 Timing Requirements: Data Read Operation

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 2)
MIN NOM MAX UNIT
tDZ_CNCS Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of data read operation during conversion 10 ns
tDZ_CSBSY Delay between CS rising edge to BUSY falling edge, end of data read operation during conversion 40 ns
tSU_BSYCS Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion 0 ns
tD_CSCN Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of data read operation after conversion 10 ns

6.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 3)
MIN NOM MAX UNIT
tPH_CS, tPH_RD CS and RD high time 15 ns
tPL_CS, tPL_RD CS and RD low time 15 ns
tHT_RDDB, tHT_CSDB Hold time: RD and CS rising edge to DB[15:0] invalid 2.5 ns

6.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 4)
MIN NOM MAX UNIT
tSU_CSRD Set-up time: CS falling edge to RD falling edge 0 ns
tHT_RDCS Hold time: RD rising edge to CS rising edge 0 ns
tPL_RD RD low time 15 ns
tPH_RD RD high time 15 ns
tHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns
tHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

6.10 Timing Requirements: Serial Data Read Operation

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 5)
MIN NOM MAX UNIT
tSCLK SCLK time period 50 ns
tPH_SCLK SCLK high time 0.45 0.55 tSCLK
tPL_SCLK SCLK low time 0.45 0.55 tSCLK
tHT_CKDO Hold time: SCLK rising edge to DOUTA, DOUTB invalid 7 ns
tSU_CSCK Setup time: CS falling to first SCLK edge 8 ns
tHT_CKCS Hold time: last SCLK active edge to CS high 10 ns

6.11 Timing Requirements: Byte Mode Data Read Operation

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 6)
MIN NOM MAX UNIT
tSU_CSRD Setup time: CS falling edge to RD falling edge 0 ns
tHT_RDCS Hold time: RD rising edge to CS rising edge 0 ns
tPL_RD RD low time 15 ns
tPH_RD RD high time 15 ns
tHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns
tHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

6.12 Timing Requirements: Oversampling Mode

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 7)
MIN NOM MAX UNIT
tHT_OS Hold time: BUSY falling to OSx 20 ns
tSU_OS Setup time: BUSY falling to OSx 20 ns

6.13 Timing Requirements: Exit Standby Mode

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C, AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 8)
MIN NOM MAX UNIT
tD_STBYCN Delay between STBY rising edge to CONVSTA or CONVSTB rising edge(1) 100 µs
(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

6.14 Timing Requirements: Exit Shutdown Mode

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 9)
MIN NOM MAX UNIT
tD_SDRST Delay between STBY rising edge to RESET rising edge Internal reference mode 50 ms
External reference mode(1) 13
tPH_RST RESET high time 50 ns
tD_RSTCN Delay between RESET falling edge to CONVSTA or CONVSTB rising edge 25 µs
(1) Excludes wake-up time for external reference device.

6.15 Switching Characteristics: CONVST Control

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCYC ADC cycle time period No oversampling, parallel read, serial read with both DOUTA and DOUTB during conversion 2 µs
No oversampling, serial read after conversion with both DOUTA and DOUTB 7.2
No oversampling, serial read after conversion with only DOUTA or DOUTB 12.5
tCONV Conversion time: BUSY high time No oversampling 1.19 1.24 1.29 µs
Oversampling by 2 3.04 3.29
Oversampling by 4 6.71 7.25
Oversampling by 8 14.04 15.18
Oversampling by 16 28.71 31.05
Oversampling by 32 58.05 62.77
Oversampling by 64 116.7 126.2
tD_CNBSY Delay between trailing rising edges of CONVSTA or CONVSTB and BUSY rising 15 ns

6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tD_CSDB, tD_RDDB Delay time: CS and RD falling edge to DB[15:0] becoming valid
(out of tri-state)		 12 ns
tD_CSFD, tD_RDFD Delay time: CS and RD falling edge to FRSTDATA going high or low out of tri-state 10 ns
tDHZ_CSDB, tDHZ_RDDB Delay time: CS and RD rising edge to DB[15:0] tri-state 12 ns
tDHZ_CSFD, tDHZ_RDFD Delay time: CS and RD rising edge to FRSTDATA tri-state 10 ns

6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tD_CSDB Delay time: CS falling edge to DB[15:0] becoming valid
(out of tri-state)		 12 ns
tD_RDDB Delay time: RD falling edge to new data on DB[15:0] 17 ns
tDHZ_CSDB Delay time: CS rising edge to DB[15:0] becoming tri-state 12 ns
tD_CSFD Delay time: CS falling edge to FRSTDATA going low out of tri-state 15 ns
tDHZ_CSFD Delay time: CS rising edge to FRSTDATA going to tri-state 10 ns
tD_RDFD Delay time: RD falling edge to FRSTDATA going high or low 15 ns

6.18 Switching Characteristics: Serial Data Read Operation

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tD_CSDO Delay time: CS falling edge to DOUTA, DOUTB enable
(out of tri-state)		 12 ns
tD_CKDO Delay time: SCLK rising edge to valid data on DOUTA, DOUTB 15 ns
tDZ_CSDO Delay time: CS rising edge to DOUTA, DOUTB going to tri-state 12 ns
tD_CSFD Delay time: CS falling edge to FRSTDATA from tri-state to high or low 10 ns
tDZ_CKFD Delay time: 18th SCLK falling edge to FRSTDATA falling edge 15 ns
tDHZ_CSFD Delay time: CS rising edge to FRSTDATA going to tri-state 10 ns

6.19 Switching Characteristics: Byte Mode Data Read Operation

minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tD_CSDB Delay time: CS falling edge to DB[7:0] becoming valid
(out of tri-state)		 12 ns
tD_RDDB Delay time: RD falling edge to new data on DB[7:0] 17 ns
tDHZ_CSDB Delay time: CS rising edge to DB[7:0] becoming tri-state 12 ns
tD_CSFD Delay time: CS falling edge to FRSTDATA going low out of tri-state 10 ns
tD_RDFD Delay time: RD falling edge to FRSTDATA going low or high state 15 ns
tDHZ_CSFD Delay time: CS rising edge to FRSTDATA going to tri-state 10 ns
ADS8598H tim_conv_ctrl_sbas642.gif Figure 1. CONVST Control Timing Diagram
ADS8598H tim_data_read_sbas642.gif Figure 2. Data Read Operation Timing Diagram
ADS8598H tim_par_data_read_CSzRD_tied_BAS827.gif Figure 3. Parallel Data Read Operation, CS and RD Tied Together
ADS8598H tim_par_data_read_CSzRD_sep_BAS827.gif Figure 4. Parallel Data Read Operation, CS and RD Separate
ADS8598H tim_serial_data_read_BAS827.gif Figure 5. Serial Data Read Operation Timing Diagram
ADS8598H tim_byte_data_read_sbas829.gif Figure 6. Byte Mode Data Read Operation Timing Diagram
ADS8598H tim_osr_pin_sbas642.gif Figure 7. Oversampling Mode Timing Diagram
ADS8598H tim_exit_standby_sbas642.gif Figure 8. Exit Standby Mode Timing Diagram
ADS8598H tim_exit_shutdown_sbas642.gif Figure 9. Exit Shutdown Mode Timing Diagram

6.20 Typical Characteristics

at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 500 kSPS per channel (unless otherwise noted)
ADS8598H D002_SBAS642.gif
Figure 10. Analog Input Current vs Input Voltage and Temperature (±10 V)
ADS8598H D004_SBAS642.gif
Figure 12. Input Impedance vs Free-Air Temperature
ADS8598H D010_SBAS829.gif
Mean = –0.11, sigma = 2.13, number of hits = 4096, VIN = 0 V
Figure 14. DC Histogram of Codes (±5 V)
ADS8598H D012_SBAS829.gif
Figure 16. DNL vs Free-Air Temperature
ADS8598H D014_SBAS829.gif
Figure 18. INL vs All Codes (±5 V)
ADS8598H D016_SBAS829.gif
Figure 20. INL vs Free-Air Temperature (±5 V)
ADS8598H D018_SBAS642.gif
Figure 22. Offset Drift Histogram Distribution (±10 V)
ADS8598H D020_SBAS642.gif
Figure 24. Offset Drift Histogram Distribution (±5 V)
ADS8598H D022_SBAS829.gif
External reference
Figure 26. Gain Error vs Temperature
ADS8598H D024_SBAS829.gif
External reference
Figure 28. Gain Error Across Channels vs Free-Air Temperature (±10 V)
ADS8598H D026_SBAS829.gif
External reference
Figure 30. Gain Error Across Channels vs Free-Air Temperature (±5 V)
ADS8598H D028_SBAS829.gif
Number of points = 256k, SNR = 94.1 dB,
SINAD = 93.8 dB, THD = –105.3, SFDR = 106.9 dB
Figure 32. Typical FFT Plot (±10 V)
ADS8598H D030_SBAS829.gif
Number of points = 256k, SNR = 101.8 dB,
SINAD = 101.1 dB, THD = –109.6 dB, SFDR = 113.3 dB
Figure 34. Typical FFT Plot for OSR 32x (±10 V)
ADS8598H D032_SBAS829.gif
OSR = 0
Figure 36. SNR vs Input Frequency for Different Input Ranges
ADS8598H D034_SBAS829.gif
Figure 38. SNR vs Input Frequency for Different OSR
(±10 V)
ADS8598H D036_SBAS829.gif
OSR = 0
Figure 40. SINAD vs Input Frequency for Different Input Ranges
ADS8598H D038_SBAS829.gif
Figure 42. THD vs Input Frequency for Different Input Ranges
ADS8598H D040_SBAS829.gif
Figure 44. THD vs Input Frequency for Different Source Impedances (±10 V)
ADS8598H D042_SBAS829.gif
Figure 46. Isolation Crosstalk vs Frequency
(Inputs Within Range)
ADS8598H D053_SBAS829.gif
Figure 48. Analog Supply Current (Operational) vs Free-Air Temperature
ADS8598H D056_SBAS642.gif
Figure 50. Analog Supply Current vs Free-Air Temperature (Standby)
ADS8598H D003_SBAS642.gif
Figure 11. Analog Input Current vs Input Voltage and Temperature (±5 V)
ADS8598H D009_SBAS829.gif
Mean = –0.11, sigma = 1.86, number of hits = 4096, VIN = 0 V
Figure 13. DC Histogram of Codes (±10 V)
ADS8598H D011_SBAS829.gif
Figure 15. DNL for All Codes
ADS8598H D013_SBAS829.gif
Figure 17. INL vs All Codes (±10 V)
ADS8598H D015_SBAS829.gif
Figure 19. INL vs Free-Air Temperature (±10 V)
ADS8598H D017_SBAS642.gif
Figure 21. Offset Error vs Free-Air Temperature
ADS8598H D019_SBAS642.gif
Figure 23. Offset Error Across Channels vs Free-Air Temperature (±10 V)
ADS8598H D021_SBAS642.gif
Figure 25. Offset Error Across Channels vs Free-Air Temperature (±5 V)
ADS8598H D023_SBAS642.gif
External reference
Figure 27. Gain Error Drift Histogram Distribution (±10 V)
ADS8598H D025_SBAS642.gif
External reference
Figure 29. Gain Error Drift Histogram Distribution (±5 V)
ADS8598H D027_SBAS829.gif
Figure 31. Gain Error as a Function of External Source Resistance
ADS8598H D029_SBAS829.gif
Number of points = 256k, SNR = 93.11 dB,
SINAD = 92.84 dB, THD = –105.07 dB, SFDR = 106.76 dB
Figure 33. Typical FFT Plot (±5 V)
ADS8598H D031_SBAS829.gif
Number of points = 256k, SNR = 98.9 dB,
SINAD = 98.5 dB, THD = –109 dB, SFDR = 114.9 dB
Figure 35. Typical FFT Plot for OSR 32x (±5 V)
ADS8598H D033_SBAS829.gif
OSR = 0
Figure 37. SNR vs Free-Air Temperature for Different Input Ranges
ADS8598H D035_SBAS829.gif
Figure 39. SNR vs Input Frequency for Different OSR
(±5 V)
ADS8598H D037_SBAS829.gif
OSR = 0
Figure 41. SINAD vs Free-Air Temperature for Different Input Ranges
ADS8598H D039_SBAS829.gif
Figure 43. THD vs Free-Air Temperature for Different Input Ranges
ADS8598H D041_SBAS829.gif
Figure 45. THD vs Input Frequency for Different Source Impedances (±5 V)
ADS8598H D043_SBAS829.gif
Figure 47. Isolation Crosstalk vs Frequency (Saturated Inputs)
ADS8598H D055_SBAS829.gif
Figure 49. Analog Supply Current (Static) vs Free-Air Temperature (Sampling)
ADS8598H D057_SBAS642.gif
Figure 51. Analog Supply Current vs Free-Air Temperature (Shutdown)