SBAS633E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)

GUID-32F1C48E-A703-4E5E-A0A1-92946F66140A-low.gif
 
Figure 6-9 Input I-V Characteristic Across Input Ranges
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Figure 6-11 Input Impedance Drift vs Temperature
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Mean = 32768.24, sigma = 0.57, input = 0 V
Figure 6-13 DC Histogram for Mid-Scale Inputs (±12.288 V)
GUID-C927CA32-8F57-4CAD-A7DD-27A70FED5F96-low.gif
Mean = 32768.21, sigma = 0.62, input = 0 V
Figure 6-15 DC Histogram for Mid-Scale Inputs (±6.144 V)
GUID-7C91A801-37E2-4C51-99DE-6002771B7034-low.gif
Mean = 32768.22, sigma = 0.75, input = 0 V
Figure 6-17 DC Histogram for Mid-Scale Inputs (±2.56 V)
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Mean = 32768.41, sigma = 0.62, input = 5.12 V
Figure 6-19 DC Histogram for Mid-Scale Inputs (0 V–10.24 V)
GUID-7548141B-8CE7-41E2-A2A0-2516082E614A-low.gif
Mean = 32768.32, sigma = 0.78, input = 2.56 V
Figure 6-21 DC Histogram for Mid-Scale Inputs (0 V–5.12 V)
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All input ranges
Figure 6-23 DNL vs Temperature
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Figure 6-25 Typical INL for All Codes (All Unipolar Ranges)
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Figure 6-27 INL vs Temperature (All Unipolar Ranges)
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Figure 6-29 Typical Histogram for Offset Drift
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Figure 6-31 Typical Histogram for Gain Error Drift
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Number of points = 64k, fIN = 1 kHz
Figure 6-33 Typical FFT Plot (All Ranges) for the ADS8681
GUID-384390B4-04C6-450D-A98A-61CF611AB366-low.gif
Number of points = 64k, fIN = 1 kHz
Figure 6-35 Typical FFT Plot (All Ranges) for the ADS8689
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fIN = 1 kHz
Figure 6-37 SNR vs Temperature
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fIN = 1 kHz
Figure 6-39 SINAD vs Temperature
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fIN = 1 kHz
Figure 6-41 THD vs Temperature
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Figure 6-43 AVDD Current vs Throughput
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Figure 6-45 AVDD Current vs Temperature (Standby Mode)
GUID-F1365E9E-6A68-4E5D-BD30-21DA5B954031-low.gif
Range = ±12.288 V
Figure 6-10 Input I-V Characteristic Across Temperature
GUID-BD8889AE-CA2F-4B20-88AA-CCE3A8E808DE-low.gif
Number of samples = 3398
Figure 6-12 Typical Distribution of Input Impedance
GUID-7CBA3A20-8992-4515-A4CA-CD28BD77B032-low.gif
Mean = 32767.24, sigma = 0.56, input = 0 V
Figure 6-14 DC Histogram for Mid-Scale Inputs (±10.24 V)
GUID-CB5C45B3-E06A-4312-8B8E-519F92D4D0B2-low.gif
Mean = 32768.11, sigma = 0.62, input = 0 V
Figure 6-16 DC Histogram for Mid-Scale Inputs (±5.12 V)
GUID-9060C8FE-03CD-4C43-9CE1-8695DB77B1F6-low.gif
Mean = 32767.73, sigma = 0.60, input = 6.144 V
Figure 6-18 DC Histogram for Mid-Scale Inputs (0 V–12.288 V)
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Mean = 32768.42, sigma = 0.76, input = 3.072 V
Figure 6-20 DC Histogram for Mid-Scale Inputs (0 V–6.144 V)
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All input ranges
Figure 6-22 Typical DNL for All Codes
GUID-D6BFF53C-E91C-44AB-9BCB-9C7D32CA3558-low.gif
 
Figure 6-24 Typical INL for All Codes (All Bipolar Ranges)
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Figure 6-26 INL vs Temperature (All Bipolar Ranges)
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Figure 6-28 Offset Error vs Temperature Across Input Ranges
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Figure 6-30 Gain Error vs Temperature Across Input Ranges
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Figure 6-32 Gain Error vs External Resistance (REXT)
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Number of points = 64k, fIN = 1 kHz
Figure 6-34 Typical FFT Plot (All Ranges) for the ADS8685
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Figure 6-36 SNR vs Input Frequency
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Figure 6-38 SINAD vs Input Frequency
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Figure 6-40 THD vs Input Frequency
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Figure 6-42 AVDD Current vs Temperature
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Figure 6-44 AVDD Current vs Temperature (During Sampling)
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Figure 6-46 AVDD Current vs Temperature (Power-Down Mode)