SBASAY5 June 2024 ADS8681W
PRODUCTION DATA
The device features the multiSPI digital interface for communication and data transfer between the device and host controller. The multiSPI interface supports many data transfer protocols that the host uses to exchange data and commands with the device. The host transfers data into the device using one of the standard SPI modes. However, the device has various configurations available to output data to meet the specific application demands of throughput and latency. The data output in these modes is controlled either by the host or the device, and the timing is either system synchronous or source synchronous. For detailed explanation of the supported data transfer protocols, see the Data Transfer Protocols section.
This section describes the main components of the digital interface module and the supported configurations and protocols. As shown in Figure 6-19, the interface module is comprised of shift registers (both input and output), configuration registers, and a protocol unit. During any particular data frame, data are transferred both into and out of the device. As a result, the host always perceives the device as a 32-bit, input-output shift register.
The Pin Configuration and Functions section provides descriptions of the interface pins. The Data Transfer Frame section details the functions of shift registers, the SCLK counter, and the command processor. The Data Transfer Frame section details supported protocols, and the Register Maps section explains the configuration registers and bit settings.