SBASAY5 June 2024 ADS8681W
PRODUCTION DATA
This register controls the data output by the device.
The address for bits 7-0, 15-8, 23-16, and 31-24 is 10h, 11h, 12h, and 13h, respectively.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0000h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | DEVICE_ ADDR_ INCL |
VDD_ACTIVE_ ALARM_INCL[1:0] |
IN_ACTIVE_ ALARM_INCL[1:0] |
Reserved | RANGE_ INCL | Reserved | PAR_EN | DATA_VAL [2:0] |
|||||||
R-0b | R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b | R-0000b | R/W-<0>b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | Reserved | R | 0000h | Reserved. Reads return 0000h. |
15 | Reserved | R | 0b | Reserved. Reads return 0b. |
14 | DEVICE_ADDR_INCL | R/W | 0b | Control to include the 4-bit DEVICE_ADDR
register value in the SDO-x output bit stream. 0b = Do not include the register value 1b = Include the register value |
13-12 | VDD_ACTIVE_ALARM_INCL[1:0] | R/W | 00b | Control to include the active VDD ALARM
flags in the SDO-x output bit stream. 00b = Do not include 01b = Include ACTIVE_VDD_H_FLAG 10b = Include ACTIVE_VDD_L_FLAG 11b = Include both flags |
11-10 | IN_ACTIVE_ALARM_INCL[1:0] | R/W | 00b | Control to include the active input ALARM
flags in the SDO-x output bit stream. 00b = Do not include 01b = Include ACTIVE_IN_H_FLAG 10b = Include ACTIVE_IN_L_FLAG 11b = Include both flags |
9 | Reserved | R | 0b | Reserved. Reads return 0h. |
8 | RANGE_INCL | R/W | 0b | Control to include the 4-bit input range
setting in the SDO-x output bit stream. 0b = Do not include the range configuration register value 1b = Include the range configuration register value |
7-4 | Reserved | R | 0000b | Reserved. Reads return 0000b. |
3 | PAR_EN(1) | R/W | 0b | 0b = Output data does not contain parity
information 1b = Two parity bits (ADC output and output data frame) are appended to the LSBs of the output data The ADC output parity bit reflects an even parity for the ADC output bits only. The output data frame parity bit reflects an even parity signature for the entire output data frame. This signature includes the ADC output bits and any internal flags or register settings. The ADC output parity bit is not included in the frame parity bit computation. |
2-0 | DATA_VAL[2:0] | R/W | 000b | These bits control the data value output by
the converter. 0xxb = Value output is the conversion data 100b = Value output is all 0's 101b = Value output is all 1's 110b = Value output is alternating 0's and 1's 111b = Value output is alternating 00's and 11's |