SBASAY5 June 2024 ADS8681W
PRODUCTION DATA
This register controls the data protocol used to transmit data out from the SDO-x pins of the device.
The address for bits 7-0, 15-8, 23-16, and 31-24 is 0Ch, 0Dh, 0Eh, and 0Fh, respectively.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0000h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | GPO_VAL | Reserved | SDO1_ CONFIG [1:0] |
Reserved | SSYNC_CLK | Reserved | SDO_ MODE[1:0] |
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R-000b | R/W-0b | R-00b | R/W-00b | R-0b | R/W-<0>b | R-0h | R/W-<0>b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | Reserved | R | 0000h | Reserved. Reads return 0h. |
15-13 | Reserved | R | 000b | Reserved. Reads return 000b. |
12 | GPO_VAL | R/W | 0b | 1-bit value for the output on the GPO pin. |
11-10 | Reserved | R | 00b | Reserved. Reads return 00b. |
9-8 | SDO1_CONFIG[1:0] | R/W | 00b | Two bits
configure
ALARM/SDO-1/GPO: 00b = SDO-1 is always tri-stated; 1-bit SDO mode 01b = SDO-1 functions as ALARM; 1-bit SDO mode 10b = SDO-1 functions as GPO; 1-bit SDO mode 11b = SDO-1 combined with SDO-0 offers a 2-bit SDO mode |
7 | Reserved | R | 0b | Reserved. Reads return 0b. |
6 | SSYNC_CLK(1) | R/W | 0b | This bit controls the
source of the clock selected for source-synchronous transmission. 0b = External SCLK (no division) 1b = Internal clock (no division) |
5-2 | Reserved | R | 0000b | Reserved. Reads return 0000b. |
1-0 | SDO_MODE[1:0] | R/W | 00b | These bits control the data
output modes of the device. 0xb = SDO mode follows the same SPI protocol as that used for SDI; see the SDI_CTL_REG register 10b = Invalid configuration 11b = SDO mode follows the ADC controller clock or source-synchronous protocol |