SBASAY5 June   2024 ADS8681W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Alarm Function
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7.1 Internal Reference

The device features an internal reference source with a nominal output value of 4.096V. To select the internal reference, program the INTREF_DIS bit of the RANGE_SEL_REG register to logic 0. When the internal reference is used, the REFIO pin becomes an output with the internal reference value. As shown in Figure 6-7, place a 4.7µF (minimum) decoupling capacitor between the REFIO and REFGND pins. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. Using a smaller capacitor value allows higher reference noise in the system that potentially degrades SNR and SINAD performance. Do not use the REFIO pin to drive external ac or dc loads because of limited current output capability. Use the REFIO pin as a source if followed by an acceptable op amp buffer (such as the OPA320).

ADS8681W ADS8685W ADS8689W Device Connections for Using an Internal 4.096V Reference Figure 6-7 Device Connections for Using an Internal 4.096V Reference

The device internal reference is factory-trimmed to provide the initial accuracy specification. The histogram in Figure 6-8 shows the distribution of the internal voltage reference output taken from more than 3420 production devices.

ADS8681W ADS8685W ADS8689W Internal Reference Accuracy Histogram at Room Temperature
 
Figure 6-8 Internal Reference Accuracy Histogram at Room Temperature

The initial accuracy specification for the internal reference is degraded if the die is exposed to any mechanical or thermal stress. Heating the device while soldering to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die stress and is a function of the package, die-attach material, molding compound, and device layout.

To illustrate this effect, 30 devices were soldered using lead-free solder paste with the manufacturer suggested reflow profile. This process is explained in the AN-2029 Handling and Process Recommendations application note. As shown in Figure 6-9, the internal voltage reference output is measured before and after the reflow process and the typical shift in value. Although all tested units exhibit a positive shift in the output voltages, negative shifts are also possible. The histogram in Figure 6-9 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS868xW in the second pass to minimize device exposure to thermal stress.

ADS8681W ADS8685W ADS8689W Solder Heat Shift Distribution Histogram
 
Figure 6-9 Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to +125°C. Figure 6-10 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. Figure 6-11 shows histogram distribution of the reference voltage drift for the WQFN (RUM) package.

ADS8681W ADS8685W ADS8689W REFIO Voltage Variation Across AVDD and Temperature
 
Figure 6-10 REFIO Voltage Variation Across AVDD and Temperature
ADS8681W ADS8685W ADS8689W Internal Reference Temperature Drift Histogram
AVDD = 5V, number of devices = 30, ΔT = –40°C to +125°C
Figure 6-11 Internal Reference Temperature Drift Histogram