SBASAY5 June   2024 ADS8681W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Alarm Function
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3 Input Protection Circuit

The device features an internal overvoltage protection (OVP) circuit on each of the analog inputs. Use the external protection devices in the end application to protect against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions. Figure 6-2 illustrates a conceptual block diagram of the internal OVP circuit.

ADS8681W ADS8685W ADS8689W Input Overvoltage Protection Circuit Schematic Figure 6-2 Input Overvoltage Protection Circuit Schematic

As shown in Figure 6-2, the combination of input resistors and PGA gain-setting resistors RFB and RDC limit the current flowing into the input pin. Use 1MΩ (or 1.2MΩ for appropriate input ranges) input resistors. A combination of antiparallel diodes, D1 and D2, are added to protect the internal circuitry and set the overvoltage protection limits.

Table 6-1 explains the various operating conditions for the device when powered on. Make sure the device is properly powered up (AVDD = 5V) or offers a low impedance of < 30kΩ. When properly set, the internal overvoltage protection circuit withstands up to ±20V on the analog input pins.

Table 6-1 Input Overvoltage Protection Limits When AVDD = 5V
INPUT CONDITION(1)
(VOVP = ±20V)		 TEST CONDITION ADC OUTPUT COMMENTS
CONDITION RANGE
|VIN| < |VRANGE| Within operating range All input ranges Valid The device functions as per data sheet specifications.
|VRANGE| < |VIN| < |VOVP| Beyond operating range but within overvoltage range All input ranges Saturated The ADC output is saturated, but the device is internally protected (not recommended for extended time).
|VIN| > |VOVP| Beyond overvoltage range All input ranges Saturated This usage condition potentially causes irreversible damage to the device.
(1) GND = 0V, AIN_M = 0V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the breakdown voltage for the internal OVP circuit. Assume that RS is approximately 0Ω.

The results indicated in Table 6-1 assume that the analog input pin is driven by a very low impedance source (RS is approximately 0Ω). However, if the source driving the input has higher impedance, the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Higher source impedances result in gain errors and contribute to overall system noise performance.

Figure 6-3 illustrates the voltage versus current response of the internal overvoltage protection circuit when the device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pin is limited by the input impedance. The input impedance is 1MΩ (or 1.2MΩ for appropriate input ranges). However, for voltages beyond ±20V, the internal node voltages surpass the breakdown voltage for internal transistors. Thus, the limit for overvoltage protection is set on the input pin.

ADS8681W ADS8685W ADS8689W I-V Curve for the Input OVP Circuit (AVDD = 5V)
 
Figure 6-3 I-V Curve for the Input OVP Circuit (AVDD = 5V)

The same overvoltage protection circuit also provides protection to the device when the device is not powered on and AVDD is floating. This condition arises when the input signals are applied before the ADC is fully powered on. Table 6-2 shows the overvoltage protection limits for this condition.

Table 6-2 Input Overvoltage Protection Limits When AVDD = Floating
INPUT CONDITION(1)
(VOVP = ±15V)		 TEST CONDITION ADC OUTPUT COMMENTS
CONDITION RANGE
|VIN| < |VOVP| Within overvoltage range All input ranges Invalid The device is not functional but is protected internally by the OVP circuit.
|VIN| > |VOVP| Beyond overvoltage range All input ranges Invalid This usage condition potentially causes irreversible damage to the device.
(1) AVDD = floating, GND = 0V, AIN_M = 0V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the breakdown voltage for the internal OVP circuit. Assume that RS is approximately 0Ω.

Figure 6-4 shows the I-V response of the internal overvoltage protection circuit when the device is not powered on. According to this I-V response, the current flowing into the device input pin is limited by the 1MΩ input impedance. However, for voltages beyond ±15V, the internal node voltage surpasses the breakdown voltage for internal transistors. Thus, the limit for overvoltage protection is set on the input pin.

ADS8681W ADS8685W ADS8689W I-V Curve for the Input OVP Circuit (AVDD = Floating)
 
Figure 6-4 I-V Curve for the Input OVP Circuit (AVDD = Floating)