SBAS633E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Input Protection Circuit

The device features an internal overvoltage protection (OVP) circuit on each of the analog inputs. Use the internal protection circuit only as a secondary protection scheme. The external protection devices in the end application are highly recommended to be used to protect against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions. A conceptual block diagram of the internal OVP circuit is shown in Figure 7-2.

GUID-4B0DBB44-462A-4B8D-9275-1CF03ABB9F94-low.gifFigure 7-2 Input Overvoltage Protection Circuit Schematic

As shown in Figure 7-2, the combination of the 1-MΩ (or, 1.2 MΩ for appropriate input ranges) input resistors along with the PGA gain-setting resistors RFB and RDC limit the current flowing into the input pin. A combination of anti-parallel diodes, D1 and D2 are added to protect the internal circuitry and set the overvoltage protection limits.

Table 7-1 explains the various operating conditions for the device when powered on. This table indicates that when the device is properly powered up (AVDD = 5 V) or offers a low impedance of < 30 kΩ, the internal overvoltage protection circuit can withstand up to ±20 V on the analog input pins.

Table 7-1 Input Overvoltage Protection Limits When AVDD = 5 V(1)
INPUT CONDITION
(VOVP = ±20 V)		TEST CONDITIONADC OUTPUTCOMMENTS
CONDITIONRANGE
|VIN| < |VRANGE|Within operating rangeAll input rangesValidDevice functions as per data sheet specifications.
|VRANGE| < |VIN| < |VOVP|Beyond operating range but within overvoltage rangeAll input rangesSaturatedADC output is saturated, but device is internally protected (not recommended for extended time).
|VIN| > |VOVP|Beyond overvoltage rangeAll input rangesSaturatedThis usage condition can cause irreversible damage to the device.
(1) GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.

The results indicated in Table 7-1 are based on an assumption that the analog input pin is driven by a very low impedance source (RS is approximately 0 Ω). However, if the source driving the input has higher impedance, the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Higher source impedances result in gain errors and contribute to overall system noise performance.

Figure 7-3 shows the voltage versus current response of the internal overvoltage protection circuit when the device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pin is limited by the 1-MΩ (or 1.2 MΩ for appropriate input ranges) input impedance. However, for voltages beyond ±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pin.

The same overvoltage protection circuit also provides protection to the device when the device is not powered on and AVDD is floating. This condition can arise when the input signals are applied before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 7-2.

Table 7-2 Input Overvoltage Protection Limits When AVDD = Floating(1)
INPUT CONDITION
(VOVP = ±15 V)		TEST CONDITIONADC OUTPUTCOMMENTS
CONDITIONRANGE
|VIN| < |VOVP|Within overvoltage rangeAll input rangesInvalidDevice is not functional but is protected internally by the OVP circuit.
|VIN| > |VOVP|Beyond overvoltage rangeAll input rangesInvalidThis usage condition can cause irreversible damage to the device.
(1) AVDD = floating, GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.

Figure 7-4 shows the I-V response of the internal overvoltage protection circuit when the device is not powered on. According to this I-V response, the current flowing into the device input pin is limited by the 1-MΩ input impedance. However, for voltages beyond ±15 V, the internal node voltage surpasses the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pin.

GUID-FF2F1B72-E8AE-4B59-8D7D-DDBFCAAE9853-low.gif
Figure 7-3 I-V Curve for the Input OVP Circuit (AVDD = 5 V)
GUID-9167A9A9-C943-45A9-8B20-59EF60BA21D7-low.gif
Figure 7-4 I-V Curve for the Input OVP Circuit (AVDD = Floating)