SBAS633E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Data Transfer Frame

A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a data transfer frame by bringing the CONVST/CS signal low (as shown in Figure 7-29) after the end of the CONV phase, as described in the Section 7.4.2.3 section.

GUID-DF2A8BBD-F540-4059-AD63-91D02B27DF5C-low.gifFigure 7-29 Data Transfer Frame

For a typical data transfer frame F:

  1. The host controller pulls CONVST/CS low to initiate a data transfer frame. On the falling edge of the CONVST/CS signal:
    • RVS goes low, indicating the beginning of the data transfer frame.
    • The internal SCLK counter is reset to 0.
    • The device takes control of the data bus. As illustrated in Figure 7-29, the contents of the output data word are loaded into the 32-bit output shift register (OSR).
    • The internal configuration register is reset to 0000h, corresponding to a NOP command.
  2. During the frame, the host controller provides clocks on the SCLK pin:
    • On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted into the LSB of the input shift register.
    • On each launch edge of the output clock (SCLK in this case), the MSB of the output shift register data is shifted out on the selected SDO-x pins.
    • The status of the RVS pin depends on the output protocol selection (see the Section 7.5.4.2 section).
  3. The host controller pulls the CONVST/CS pin high to end the data transfer frame. On the rising edge of CONVST/CS:
    • The SDO-x pins go to tri-state.
    • As illustrated in Figure 7-29, the contents of the input shift register are transferred to the command processor for decoding and further action.
    • RVS output goes low, indicating the beginning of conversion.

After pulling CONVST/CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max time (see the Section 6.6 table) to elapse before initiating a new data transfer frame.

At the end of the data transfer frame F:

  • If the SCLK counter = 32, then the device treats the frame F as an optimal data transfer frame for any read or write operation. At the end of an optimal data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word.
  • If the SCLK counter is < 32, then the device treats the frame F as a short data transfer frame.
    • The data write operation to the device in invalid and the device treats this frame as an NOP command.
    • The output data bits transferred during a short frame on the SDO-x pins are still valid data. The host controller can use the short data transfer frame to read only the required number of MSB bits from the 32-bit output shift register.
  • If the SCLK counter is > 32, then the device treats the frame F as a long data transfer frame. At the end of a long data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, when the host controller provides a long data transfer frame, the last 32 bits shifted into the device prior to the CONVST/CS rising edge must constitute the desired command.