SBAS633E February 2016 – August 2022 ADS8681 , ADS8685 , ADS8689
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The device features a programmable gain amplifier (PGA) as part of the analog signal-conditioning circuit that converts the original single-ended input signal into a fully-differential signal to drive the internal SAR ADC. The PGA also adjusts the common-mode level of the input signal before the signal is fed into the SAR ADC to ensure maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be adjusted by setting the RANGE_SEL[3:0] bits in the configuration register (see the RANGE_SEL_REG register). The default or power-on state for the RANGE_SEL[3:0] bits is 0000, corresponding to an input signal range of ±3 × VREF. Table 7-3 lists the various configurations of the RANGE_SEL[3:0] bits for the different analog input voltage ranges.
The PGA uses a precisely-matched network of resistors for multiple gain configurations. Matching between these resistors is accurately trimmed to keep the overall gain error low across all input ranges.
ANALOG INPUT RANGE | RANGE_SEL[3:0] | |||
---|---|---|---|---|
BIT 3 | BIT 2 | BIT 1 | BIT 0 | |
±3 × VREF | 0 | 0 | 0 | 0 |
±2.5 × VREF | 0 | 0 | 0 | 1 |
±1.5 × VREF | 0 | 0 | 1 | 0 |
±1.25 × VREF | 0 | 0 | 1 | 1 |
±0.625 × VREF | 0 | 1 | 0 | 0 |
0–3 × VREF | 1 | 0 | 0 | 0 |
0–2.5 × VREF | 1 | 0 | 0 | 1 |
0–1.5 × VREF | 1 | 0 | 1 | 0 |
0–1.25 × VREF | 1 | 0 | 1 | 1 |