SBAS633E February 2016 – August 2022 ADS8681 , ADS8685 , ADS8689
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with any of the data transfer protocols. In order to operate the device in dual SDO mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/SDO-1/GPO pin functions as SDO-1.
In dual SDO mode, two bits of data are launched on the two SDO-x pins (SDO-0 and SDO-1) on every SCLK launch edge, as shown in Figure 7-34 and Figure 7-35.
For any particular SPI protocol, the device follows the same timing specifications for single and dual SDO modes. The only difference is that the device requires half as many SCLK cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required SCLK frequency for a certain sampling rate of the ADC.