JAJSEC1 データシート

SBAS905C November 2019 – July 2020 ADS8686S

PRODUCTION DATA

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Mechanical Data (Package|Pins)

PZA|80
- MPQF099B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.6 Timing Requirements

At AVDD = 5 V, DVDD = 1.71 V to 5.25 V, V_IL and V_IH at datasheet limits, and f_SAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values are at T_A = –40°C to +125°C; typical values are at T_A = 25°C.

		MIN	MAX	UNIT
DEVICE CONFIGURATION
t_{D_ CSCNV}	Delay time: CS rising edge to CONVST rising edge	50		ns
t_{SU_CHXCNV}	Setup time: CHSELx to CONVST rising edge	50		ns
t_{HT_BSYCHX}	Hold time: BUSY falling edge to CHSELx change	20		ns
t_PWRUP	Power supplies settled to RESET rising edge	1		ms
t_{DEV_WRITE}	Partial reset: RESET rising edge to first falling edge of CS	50		ns
t_{DEV_WRITE}	Full reset: RESET rising edge to first falling edge of CS	240		µs
t_{SU_ RST}	Partial reset: setup time HW mode configuration inputs to RESET rising edge	10		ns
t_{SU_ RST}	Full reset: setup time HW mode configuration inputs to RESET rising edge	50		µs
t_{HT_ RST}	Partial reset: hold time RESET rising edge to HW mode configuration inputs	10		ns
t_{HT_ RST}	Full reset: Hold time RESET rising edge to HW mode configuration inputs	240		µs
CONVST CONTROL
t_ACQ	Acquisition time: BUSY falling edge to rising edge of trailing CONVST	480		ns
t_{PH_CNV}	CONVST pulse high time	50		ns
t_{PL_CNV}	CONVST pulse low time	50		ns
t_{DEV_STRTUP}	Partial reset setup time: RESET rising edge to first rising edge of CONVST	50		ns
t_{DEV_STRTUP}	Full reset setup time: RESET rising edge to first rising edge of CONVST	15		ms
t_{PL_ RST}	Partial reset	40	500	ns
t_{PL_ RST}	Full reset	1.2		µs
DATA READ
t_{SU_BSY CS}	Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion	20		ns
t_{DZ_ CSCNV}	Delay between CS rising edge to CONVST rising edge, end of data read operation after conversion	50		ns
PARALLEL AND BYTE DATA READ
t_{SU_ CSRD}	Setup time: CS falling edge to RD falling edge	10		ns
t_{HT_ RDCS}	Hold time: RD rising edge to CS rising edge	10		ns
t_{PH_ RD}	RD high time	10		ns
t_{PL_ RD}	RD low time	30		ns
SERIAL DATA READ
t_SCLK	SCLK time period, 1.71 V ≤ DVDD ≤ 2.3 V	50		ns
	SCLK time period, 2.3 V < DVDD ≤ 3 V	25		ns
	SCLK time period, DVDD > 3 V	20		ns
t_{PH_SCLK}	SCLK high time	0.45	0.55	t_SCLK
t_{PL_SCLK}	SCLK low time	0.45	0.55	t_SCLK
t_{SU_ CSCK}	Setup time: CS falling edge to SCLK falling edge DVDD > 3V	10.5		ns
	Setup time: CS falling edge to SCLK falling edge 2.3 V < DVDD ≤ 3 V	13.5		ns
	Setup time: CS falling edge to SCLK falling edge 1.71 V ≤ DVDD ≤ 2.3 V	20		ns
t_{HT_CK CS}	Hold time: SCLK to CS rising time	10		ns
PARALLEL AND BYTE DATA WRITE
t_{SU_ CSWR}	Setup time: CS falling edge to WR falling edge	10		ns
t_{HT_ WRCS}	Hold time: WR rising edge to CS rising edge	10		ns
t_{PH_ WR}	WR high time	20		ns
t_{PL_ WR}	WR low time	30		ns
t_{SU_DIN WR}	Setup time: DIN change to WR rising edge	30		ns
t_{HT_ WRDIN}	Hold time: WR rising edge to DIN change	10		ns
t_{DZ_CONFIG}	Device configuration time: WR rising edge to CONVST rising edge	20		ns
SERIAL DATA WRITE
t_{SU_DINCK}	Setup time: DIN to SCLK falling edge	10		ns
t_{HT_CKDIN}	Hold time: SCLK falling edge to DIN change	8		ns