SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog input channel of the device. During transition from one channel of the multiplexer to another channel, the fast integrated driver ensures that the multiplexer output settles to a 16-bit accuracy within the acquisition time of the ADC, irrespective of the input levels on the respective channels.