SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
As explained in the Data Acquisition Example section, the device digital interface is designed such that each data frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit command word on the SDI line. The device waits to execute the command until the last bit of the command is received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If the CS signal goes high for any reason before the data transmission is complete, the device goes into an INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid data on the SDO line. The output of the ALARM pin continues to reflect the status of input signal on the previously selected channel.