SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
The device has an internal 4.096-V (nominal value) reference. In order to select the internal reference, the REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5) becomes an output pin with the internal reference value. Figure 71 shows that placing a 10-µF (minimum) decoupling capacitor between the REFIO pin and REFGND (pin 6) is recommended. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such as the OPA320).
The device internal reference is trimmed to a maximum initial accuracy of ±1 mV. The histogram in Figure 72 shows the distribution of the internal voltage reference output taken from more than 3300 production devices.
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device itself.
In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer suggested reflow profile, as explained in application report SNOA550. The internal voltage reference output is measured before and after the reflow process and Figure 73 shows the typical shift in value. Although all tested units exhibit a positive shift in their output voltages, negative shifts are also possible. The histogram in Figure 73 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8688AT in the later pass to minimize device exposure to thermal stress.
The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –55°C to +125°C. Figure 74 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the reference voltage drift over temperature is 6 ppm/°C (Figure 75) and the maximum specified temperature drift is equal to 17 ppm/°C.
AVDD = 5 V, number of devices = 30, ΔT = –55°C to +125°C |