SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low as well. The device receives the command (see Table 8 and Table 9) through SDI where the first seven bits (bits 15-9) represent the register address and the eighth bit (bit 8) is the write or read instruction.
For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback allows verification to determine if the correct data are entered into the device. Figure 103 shows a typical timing diagram for a program register write cycle.
PIN | REGISTER ADDRESS
(Bits 15-9) |
WR/RD
(Bit 8) |
DATA
(Bits 7-0) |
---|---|---|---|
SDI | ADDR[6:0] | 1 | DIN[7:0] |
For a read cycle, the next eight bits (bits 7-0) on SDI are don’t care bits and SDO stays low. From the 16th SCLK falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in MSB-first fashion. Figure 104 shows a typical timing diagram for a program register read cycle.
PIN | REGISTER ADDRESS
(Bits 15-9) |
WR/RD
(Bit 8) |
DATA
(Bits 7-0) |
---|---|---|---|
SDI | ADDR[6:0] | 0 | XXXXX |
SDO | 0000 000 | 0 | DOUT[7:0] |