SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
The device offers a programmable gain amplifier (PGA) at each individual analog input channel, which converts the original single-ended input signal into a fully differential signal to drive the internal 16-bit ADC. The PGA also adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly adjusted by setting the Range_CHn[3:0] (n = 0 to 7) bits in the program register. The default or power-on state for the Range_CHn[3:0] bits is 0000, which corresponds to an input signal range of ±2.5 × VREF. Table 3 lists the various configurations of the Range_CHn[3:0] bits for the different analog input voltage ranges.
The PGA uses a very highly matched network of resistors for multiple gain configurations. Matching between these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low across all channels and input ranges.
ANALOG INPUT RANGE (V) | Range_CHn[3:0] | |||
---|---|---|---|---|
BIT 3 | BIT 2 | BIT 1 | BIT 0 | |
±2.5 × VREF | 0 | 0 | 0 | 0 |
±1.25 × VREF | 0 | 0 | 0 | 1 |
±0.625 × VREF | 0 | 0 | 1 | 0 |
±0.3125 × VREF | 0 | 0 | 1 | 1 |
±0.15625 × VREF | 1 | 0 | 1 | 1 |
0 to 2.5 × VREF | 0 | 1 | 0 | 1 |
0 to 1.25 × VREF | 0 | 1 | 1 | 0 |
0 to 0.625 × VREF | 0 | 1 | 1 | 1 |
0 to 0.3125 × VREF | 1 | 1 | 1 | 1 |