SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
RST/PD is a dual-function pin. Figure 86 shows the timing of this pin and Table 5 explains the usage of this pin.
CONDITION | DEVICE MODE |
---|---|
40 ns < tPL_RST_PD ≤ 100 ns | The device is in RST mode and does not enter PWR_DN mode. |
100 ns < tPL_RST_PD< 400 ns | The device is in RST mode and may or may not enter PWR_DN mode.
This setting is not recommended. |
tPL_RST_PD ≥ 400 ns | The device enters PWR_DN mode and the program registers are reset to default value. |
The device can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for at least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time regardless of the status of other pins (including the analog input channels). When the device is in power-down mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.
The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back to a logic high state, the device is placed in normal mode. One valid write operation must be executed on the program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to initiate conversions.
When the RST/PD pin is pulled back to a logic high level, the device wakes-up in a default state in which the program registers are reset to their default values.