SBAS633E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Analog Input Structure

The device features a pseudo-differential input structure, meaning that the single-ended analog input signal is applied at the positive input AIN_P and the negative input AIN_GND is tied to GND. Figure 7-1 shows the simplified circuit schematic for the AFE circuit, including the input overvoltage protection circuit, PGA, low-pass filter (LPF), and high-speed ADC driver.

GUID-5BFEA643-A44F-4F78-ADDF-678BE5E9764C-low.gifFigure 7-1 Simplified Analog Front-End Circuit Schematic

The device can support multiple unipolar or bipolar, single-ended input voltage ranges based on the configuration of the program registers. As explained in the RANGE_SEL_REG register, the input voltage range can be configured to bipolar ±3 × VREF, ±2.5 × VREF, ±1.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or unipolar 0 to 3 × VREF, 0 to 2.5 × VREF, 0 to 1.5 × VREF and 0 to 1.25 × VREF. With the internal or external reference voltage set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V or unipolar ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V.

The device samples the voltage difference (AIN_P – AIN_GND) between the analog input and the AIN_GND pin. The device allows a ±0.1-V range on the AIN_GND pin. This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_GND pin of the device to the sensor or signal-conditioning ground is recommended. In order to obtain optimum performance, the input currents and impedances along each input path are recommended to be matched. The two single-ended signals to AIN_P and AIN_GND must be routed as symmetrically as possible from the signal source to the ADC input pins.

If the analog input pin (AIN_P) to the device is left floating, the output of the ADC corresponds to an internal biasing voltage. The output from the ADC must be considered as invalid if the device is operated with floating input pins. This condition does not cause any damage to the device, which becomes fully functional when a valid input voltage is applied to the pins.