SBAS777B December   2016  – March 2021 ADS8691 , ADS8695 , ADS8699

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 Power-Down (PD) Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

The design uses galvanic isolation between the DAQ system inputs and main power supply to achieve extremely high CMRR, as indicated by Figure 8-1. The system not only tolerates large common-mode voltages beyond its absolute maximum ratings but also delivers excellent performance largely independent of common-mode amplitude and frequency (within the specified operating limits). The relevant performance characteristics are illustrated in Figure 8-9, Figure 8-3, and Figure 8-4.

The system performance requirements by itself can be easily satisfied by using the ADS869x. This device simplifies system design because the ADS869x eliminates the need for designing a discrete high-performance signal chain needed with most other SAR ADCs. In addition, the use of galvanic isolation has the following system design implications:

  • A local floating supply is needed to power the ADS869x because the device cannot load the system main power supply
  • A digital isolator is required to facilitate data transfer between the isolated ADS869x serial interface and the digital host controller

The floating power supply can be realized as an isolated transformer-based, push-pull converter followed by a rectifier and low-dropout (LDO) regulator to largely eliminate the ADC power-supply ripple by taking advantage of the high PSRR provided by most LDOs. A schematic of this design is shown in Figure 8-2.

GUID-59A4F149-ACE9-4560-B882-06C5DE8146EF-low.gif Figure 8-2 Isolated Power-Supply Design

Recommended components for the circuit shown in Figure 8-2 are given below:

  • The SN6501 transformer driver is selected for its low input voltage requirement, small form-factor, and the flexibility offered for easily adjusting the system isolation voltage rating by substituting the transformer
  • A miniature printed circuit board (PCB)-mount, center-tapped transformer with a gain > 1 maintains line regulation at the LDO outputs
  • Schottky rectifiers for minimal forward voltage drop
  • Smoothing capacitor for sufficiently low ripple at the LDO input
  • The TPS7A4901 LDOs for an ultra-low noise contribution relative to the ADS869x and high PSRR over a wide frequency range to attenuate output ripple to levels below the LDO output noise level

With regard to the digital isolator, the ISO7640FM is recommended for the following reasons:

  • Supports > a 50-MHz SCLK and the required logic levels for operating the ADS869x at the full throughput
  • Quad-channel device that facilitates excellent delay-matching between critical interface signals for reliable operation at high speed