SBAS569B May   2013  – February 2019 ADS8860

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      No Separate LDO Required for the ADC Supply
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 3-Wire Operation
    7. 7.7 Timing Requirements: 4-Wire Operation
    8. 7.8 Timing Requirements: Daisy-Chain
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Reference
      3. 9.3.3 Clock
      4. 9.3.4 ADC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode
        1. 9.4.1.1 3-Wire CS Mode Without a Busy Indicator
        2. 9.4.1.2 3-Wire CS Mode With a Busy Indicator
        3. 9.4.1.3 4-Wire CS Mode Without a Busy Indicator
        4. 9.4.1.4 4-Wire CS Mode With a Busy Indicator
      2. 9.4.2 Daisy-Chain Mode
        1. 9.4.2.1 Daisy-Chain Mode Without a Busy Indicator
        2. 9.4.2.2 Daisy-Chain Mode With a Busy Indicator
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 Charge-Kickback Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for a 1-µs, Full-Scale Step Response
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Power Saving
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS over the operating free-air temperature range (unless otherwise noted); typical specifications are at TA = 25°C, AVDD = 3 V, and DVDD = 3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) AINP – AINN 0 VREF V
Operating input range(1) AINP –0.1 VREF + 0.1 V
AINN –0.1 + 0.1
CI Input capacitance AINP and AINN terminal to GND 59 pF
Input leakage current During acquisition for dc input 5 nA
EXTERNAL REFERENCE INPUT
VREF Input range 2.5 5 V
Reference input current During conversion, 1-MHz sample rate, mid-code 300 μA
Reference leakage current 250 nA
CREF Decoupling capacitor at the REF input 10 22 µF
SYSTEM PERFORMANCE
Resolution 16 Bits
NMC No missing codes 16 Bits
DNL Differential linearity –0.99 ±0.6 1 LSB(2)
INL Integral linearity(5) –2 ±0.8 2 LSB(2)
EO Offset error(3) –4 ±1 4 mV
Offset error drift with temperature ±1.5 µV/°C
EG Gain error –0.01 ±0.005 0.01 %FSR
Gain error drift with temperature ±0.15 ppm/°C
CMRR Common-mode rejection ratio With common-mode input signal = 5 VPP at dc 90 100 dB
PSRR Power-supply rejection ratio At mid-code 80 dB
Transition noise 0.5 LSB
SAMPLING DYNAMICS
tconv Conversion time 500 710 ns
tACQ Acquisition time 290 ns
Maximum throughput rate
with or without latency		 1000 kHz
Aperture delay 4 ns
Aperture jitter, RMS 5 ps
Step response Settling to 16-bit accuracy 290 ns
Overvoltage recovery Settling to 16-bit accuracy 290 ns
DYNAMIC CHARACTERISTICS
SINAD Signal-to-noise + distortion(7) At 1 kHz, VREF = 5 V 90.5 92.9 dB
At 10 kHz, VREF = 5 V 92.9
At 100 kHz, VREF = 5 V 88.2
SNR Signal-to-noise ratio(7) At 1 kHz, VREF = 5 V 92 93 dB
At 10 kHz, VREF = 5 V 93
At 100 kHz, VREF = 5 V 88.5
THD Total harmonic distortion(7)(4) At 1 kHz, VREF = 5 V –108 dB
At 10 kHz, VREF = 5 V –108
At , VREF = 5 V –101
SFDR Spurious-free dynamic range(7) At 1 kHz, VREF = 5 V 108 dB
At 10 kHz, VREF = 5 V 108
At 100 kHz, VREF = 5 V 101
BW–3dB –3-dB small-signal bandwidth 30 MHz
POWER-SUPPLY REQUIREMENTS
Power-supply voltage AVDD Analog supply 2.7 3 3.6 V
DVDD Digital supply range for SCLK > 40 MHz 2.7 3 3.6
Digital supply range for SCLK < 40 MHz 1.65 1.8 3.6
Supply current AVDD 1-MHz sample rate, AVDD = 3 V 1.8 2.4 mA
PVA Power dissipation 1-MHz sample rate, AVDD = 3 V 5.5 7.2 mW
100-kHz sample rate, AVDD = 3 V 0.55
10-kHz sample rate, AVDD = 3 V 55 μW
IAPD Device power-down current(6) 50 nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
VIH High-level input voltage 1.65 V < DVDD < 2.3 V 0.8 × DVDD DVDD + 0.3 V
2.3 V < DVDD < 3.6 V 0.7 × DVDD DVDD + 0.3
VIL Low-level input voltage 1.65 V < DVDD < 2.3 V –0.3 0.2 × DVDD V
2.3 V < DVDD < 3.6 V –0.3 0.3 × DVDD
ILK Digital input leakage current ±10 ±100 nA
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
VOH High-level output voltage IO = 500-μA source, CLOAD = 20 pF 0.8 × DVDD DVDD V
VOL Low-level output voltage IO = 500-μA sink, CLOAD = 20 pF 0 0.2 × DVDD V
TEMPERATURE RANGE
TA Operating free-air temperature –40 85 °C
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit. 1 LSB at 16-bits is approximately 15.26 ppm.
(3) Measured relative to actual measured reference.
(4) Calculated on the first nine harmonics of the input frequency.
(5) This parameter is the endpoint INL, not best-fit.
(6) The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.
(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.